Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146720898	1			T1	18100		T2	558		T3	928
instr_valid_dis	116637460	1			T1	18100		T2	558		T3	928
instr_en	21845490	1			T17	222762		T14	179686		T8	128522

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11087358	1			T14	206370		T8	62212		T28	134
sram_ifetch_valid_disable	113108819	1			T1	18100		T2	558		T3	928
sram_ifetch_enable	22524721	1			T17	82110		T14	372650		T8	37412

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146720898	1			T1	18100		T2	558		T3	928
hw_debug_en_valid_off	113235253	1			T1	18100		T2	558		T3	928
hw_debug_en_on	22901640	1			T17	161624		T14	551446		T8	36388

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113108819	1			T1	18100		T2	558		T3	928
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101119211	1			T1	18100		T2	558		T3	928
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8347734	1			T17	140652		T14	73540		T8	35776
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4459262	1			T14	78710		T8	39330		T28	134
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2082494	1			T14	16030		T28	134		T52	43222
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1699420	1			T14	19898		T8	39330		T59	8524
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4749442	1			T14	107660		T44	36262		T59	20426
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2178690	1			T14	107660		T44	14688		T26	4240
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1819950	1			T44	21574		T59	20426		T24	84142
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9020846	1			T17	91828		T14	187952		T8	26690
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3852586	1			T14	137388		T52	10436		T59	65660
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3446396	1			T17	91828		T14	50564		T8	15776

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9185878	1			T17	82110		T14	86248		T8	30534
lc_exec_en	9131352	1			T17	69796		T14	255834		T8	9698
valid_exec_dis	110303534	1			T1	18100		T2	558		T3	928
invalid_exec_dis	33612079	1			T17	82110		T14	579020		T8	99624