| T795 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3044104457 |
|
|
Apr 21 01:13:07 PM PDT 24 |
Apr 21 01:15:17 PM PDT 24 |
5664669056 ps |
| T796 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3849678075 |
|
|
Apr 21 01:15:04 PM PDT 24 |
Apr 21 01:16:19 PM PDT 24 |
195686816 ps |
| T797 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3833663515 |
|
|
Apr 21 01:09:32 PM PDT 24 |
Apr 21 01:16:09 PM PDT 24 |
82213301305 ps |
| T798 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3571893130 |
|
|
Apr 21 01:09:43 PM PDT 24 |
Apr 21 01:09:44 PM PDT 24 |
76961781 ps |
| T799 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.968885336 |
|
|
Apr 21 01:09:10 PM PDT 24 |
Apr 21 01:09:16 PM PDT 24 |
1342309384 ps |
| T800 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1428992270 |
|
|
Apr 21 01:11:53 PM PDT 24 |
Apr 21 01:11:53 PM PDT 24 |
50963009 ps |
| T801 |
/workspace/coverage/default/34.sram_ctrl_stress_all.762153329 |
|
|
Apr 21 01:12:35 PM PDT 24 |
Apr 21 01:41:25 PM PDT 24 |
10195616087 ps |
| T802 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2190006618 |
|
|
Apr 21 01:14:16 PM PDT 24 |
Apr 21 01:14:23 PM PDT 24 |
471522372 ps |
| T803 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2535884338 |
|
|
Apr 21 01:13:49 PM PDT 24 |
Apr 21 01:16:11 PM PDT 24 |
4688946311 ps |
| T804 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3230605147 |
|
|
Apr 21 01:10:09 PM PDT 24 |
Apr 21 01:10:27 PM PDT 24 |
286727708 ps |
| T805 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2986711384 |
|
|
Apr 21 01:10:30 PM PDT 24 |
Apr 21 01:10:37 PM PDT 24 |
840769721 ps |
| T806 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.4237660596 |
|
|
Apr 21 01:10:33 PM PDT 24 |
Apr 21 01:18:52 PM PDT 24 |
21806852327 ps |
| T807 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4072549266 |
|
|
Apr 21 01:09:14 PM PDT 24 |
Apr 21 01:09:20 PM PDT 24 |
873833711 ps |
| T808 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1416926858 |
|
|
Apr 21 01:09:49 PM PDT 24 |
Apr 21 01:09:50 PM PDT 24 |
91845426 ps |
| T809 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3930604729 |
|
|
Apr 21 01:10:06 PM PDT 24 |
Apr 21 01:17:18 PM PDT 24 |
283511251056 ps |
| T810 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3847995346 |
|
|
Apr 21 01:12:30 PM PDT 24 |
Apr 21 01:12:35 PM PDT 24 |
152588501 ps |
| T811 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1781841516 |
|
|
Apr 21 01:15:03 PM PDT 24 |
Apr 21 01:16:34 PM PDT 24 |
251833519 ps |
| T812 |
/workspace/coverage/default/47.sram_ctrl_smoke.3461587752 |
|
|
Apr 21 01:14:51 PM PDT 24 |
Apr 21 01:17:17 PM PDT 24 |
708758705 ps |
| T813 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.991223713 |
|
|
Apr 21 01:11:50 PM PDT 24 |
Apr 21 01:12:33 PM PDT 24 |
106725040 ps |
| T814 |
/workspace/coverage/default/18.sram_ctrl_partial_access.976112877 |
|
|
Apr 21 01:10:18 PM PDT 24 |
Apr 21 01:10:34 PM PDT 24 |
137047857 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2683996137 |
|
|
Apr 21 01:10:48 PM PDT 24 |
Apr 21 01:10:54 PM PDT 24 |
485387714 ps |
| T816 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.68284615 |
|
|
Apr 21 01:14:28 PM PDT 24 |
Apr 21 01:14:53 PM PDT 24 |
346838627 ps |
| T817 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3376892463 |
|
|
Apr 21 01:11:17 PM PDT 24 |
Apr 21 01:16:17 PM PDT 24 |
28238632833 ps |
| T818 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2760328273 |
|
|
Apr 21 01:15:15 PM PDT 24 |
Apr 21 01:26:39 PM PDT 24 |
2636829190 ps |
| T819 |
/workspace/coverage/default/41.sram_ctrl_bijection.972232458 |
|
|
Apr 21 01:13:40 PM PDT 24 |
Apr 21 01:14:58 PM PDT 24 |
13357644605 ps |
| T820 |
/workspace/coverage/default/44.sram_ctrl_bijection.4112225157 |
|
|
Apr 21 01:14:20 PM PDT 24 |
Apr 21 01:15:07 PM PDT 24 |
1567574252 ps |
| T821 |
/workspace/coverage/default/49.sram_ctrl_executable.4190916580 |
|
|
Apr 21 01:15:27 PM PDT 24 |
Apr 21 01:26:45 PM PDT 24 |
97393367401 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4284507524 |
|
|
Apr 21 01:09:33 PM PDT 24 |
Apr 21 01:09:39 PM PDT 24 |
176225668 ps |
| T823 |
/workspace/coverage/default/24.sram_ctrl_smoke.950400431 |
|
|
Apr 21 01:10:57 PM PDT 24 |
Apr 21 01:11:06 PM PDT 24 |
939913817 ps |
| T824 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4008034791 |
|
|
Apr 21 01:14:55 PM PDT 24 |
Apr 21 01:15:05 PM PDT 24 |
94620536 ps |
| T825 |
/workspace/coverage/default/15.sram_ctrl_alert_test.769330807 |
|
|
Apr 21 01:10:06 PM PDT 24 |
Apr 21 01:10:07 PM PDT 24 |
16647496 ps |
| T826 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1244420914 |
|
|
Apr 21 01:09:42 PM PDT 24 |
Apr 21 01:09:48 PM PDT 24 |
237526653 ps |
| T827 |
/workspace/coverage/default/42.sram_ctrl_executable.96619112 |
|
|
Apr 21 01:14:02 PM PDT 24 |
Apr 21 01:27:54 PM PDT 24 |
46017303109 ps |
| T33 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.311232275 |
|
|
Apr 21 01:09:07 PM PDT 24 |
Apr 21 01:09:09 PM PDT 24 |
370495037 ps |
| T828 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3184092816 |
|
|
Apr 21 01:10:06 PM PDT 24 |
Apr 21 01:10:08 PM PDT 24 |
80409701 ps |
| T829 |
/workspace/coverage/default/23.sram_ctrl_smoke.950023330 |
|
|
Apr 21 01:10:46 PM PDT 24 |
Apr 21 01:11:28 PM PDT 24 |
655786641 ps |
| T830 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2911519061 |
|
|
Apr 21 01:09:46 PM PDT 24 |
Apr 21 01:15:00 PM PDT 24 |
151154433470 ps |
| T831 |
/workspace/coverage/default/12.sram_ctrl_smoke.2700360208 |
|
|
Apr 21 01:09:47 PM PDT 24 |
Apr 21 01:09:51 PM PDT 24 |
624167160 ps |
| T832 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1811629036 |
|
|
Apr 21 01:09:47 PM PDT 24 |
Apr 21 01:09:48 PM PDT 24 |
13826248 ps |
| T833 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1507862705 |
|
|
Apr 21 01:10:05 PM PDT 24 |
Apr 21 01:29:59 PM PDT 24 |
54976219535 ps |
| T834 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.4247991959 |
|
|
Apr 21 01:10:59 PM PDT 24 |
Apr 21 01:12:02 PM PDT 24 |
120997482 ps |
| T835 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3641342032 |
|
|
Apr 21 01:13:22 PM PDT 24 |
Apr 21 01:13:24 PM PDT 24 |
41502990 ps |
| T836 |
/workspace/coverage/default/43.sram_ctrl_stress_all.2716757120 |
|
|
Apr 21 01:14:15 PM PDT 24 |
Apr 21 02:10:32 PM PDT 24 |
130190498583 ps |
| T837 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.3766694366 |
|
|
Apr 21 01:13:07 PM PDT 24 |
Apr 21 01:13:08 PM PDT 24 |
31072346 ps |
| T838 |
/workspace/coverage/default/37.sram_ctrl_executable.17522108 |
|
|
Apr 21 01:13:03 PM PDT 24 |
Apr 21 01:15:05 PM PDT 24 |
1223988860 ps |
| T839 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3244703219 |
|
|
Apr 21 01:10:42 PM PDT 24 |
Apr 21 01:25:25 PM PDT 24 |
15350530773 ps |
| T840 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2650130791 |
|
|
Apr 21 01:10:03 PM PDT 24 |
Apr 21 01:10:39 PM PDT 24 |
665536848 ps |
| T841 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1272265340 |
|
|
Apr 21 01:09:03 PM PDT 24 |
Apr 21 01:09:12 PM PDT 24 |
235563248 ps |
| T842 |
/workspace/coverage/default/29.sram_ctrl_smoke.3967228802 |
|
|
Apr 21 01:11:36 PM PDT 24 |
Apr 21 01:11:52 PM PDT 24 |
1062229459 ps |
| T843 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2871053754 |
|
|
Apr 21 01:11:07 PM PDT 24 |
Apr 21 01:12:36 PM PDT 24 |
444600189 ps |
| T844 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2309627570 |
|
|
Apr 21 01:09:12 PM PDT 24 |
Apr 21 01:09:12 PM PDT 24 |
12762219 ps |
| T845 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1629092883 |
|
|
Apr 21 01:10:42 PM PDT 24 |
Apr 21 01:10:43 PM PDT 24 |
18017137 ps |
| T846 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3729414557 |
|
|
Apr 21 01:15:24 PM PDT 24 |
Apr 21 01:17:36 PM PDT 24 |
1383531745 ps |
| T847 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3854513529 |
|
|
Apr 21 01:13:44 PM PDT 24 |
Apr 21 01:14:09 PM PDT 24 |
86656426 ps |
| T848 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2414132487 |
|
|
Apr 21 01:13:27 PM PDT 24 |
Apr 21 01:13:28 PM PDT 24 |
231101522 ps |
| T849 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1549405371 |
|
|
Apr 21 01:09:34 PM PDT 24 |
Apr 21 01:09:42 PM PDT 24 |
544272239 ps |
| T850 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1057853918 |
|
|
Apr 21 01:09:42 PM PDT 24 |
Apr 21 01:35:30 PM PDT 24 |
58205804726 ps |
| T851 |
/workspace/coverage/default/28.sram_ctrl_bijection.1646341532 |
|
|
Apr 21 01:11:26 PM PDT 24 |
Apr 21 01:11:50 PM PDT 24 |
4071339888 ps |
| T852 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3889799209 |
|
|
Apr 21 01:12:27 PM PDT 24 |
Apr 21 01:12:28 PM PDT 24 |
64341215 ps |
| T853 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.531972554 |
|
|
Apr 21 01:10:11 PM PDT 24 |
Apr 21 01:10:19 PM PDT 24 |
1706906152 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_executable.2133111105 |
|
|
Apr 21 01:09:44 PM PDT 24 |
Apr 21 01:21:54 PM PDT 24 |
24824534941 ps |
| T855 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3653144168 |
|
|
Apr 21 01:12:05 PM PDT 24 |
Apr 21 01:20:21 PM PDT 24 |
38713540441 ps |
| T856 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3103036765 |
|
|
Apr 21 01:09:50 PM PDT 24 |
Apr 21 01:09:55 PM PDT 24 |
354721802 ps |
| T857 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.109639974 |
|
|
Apr 21 01:14:18 PM PDT 24 |
Apr 21 01:20:33 PM PDT 24 |
2898688541 ps |
| T858 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2945597282 |
|
|
Apr 21 01:10:32 PM PDT 24 |
Apr 21 01:14:43 PM PDT 24 |
10033147989 ps |
| T859 |
/workspace/coverage/default/40.sram_ctrl_smoke.2895097271 |
|
|
Apr 21 01:13:32 PM PDT 24 |
Apr 21 01:13:39 PM PDT 24 |
373401280 ps |
| T860 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.573441943 |
|
|
Apr 21 01:10:14 PM PDT 24 |
Apr 21 01:10:15 PM PDT 24 |
66570822 ps |
| T861 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2316696865 |
|
|
Apr 21 01:13:55 PM PDT 24 |
Apr 21 01:14:58 PM PDT 24 |
115882790 ps |
| T862 |
/workspace/coverage/default/18.sram_ctrl_bijection.3560832314 |
|
|
Apr 21 01:10:18 PM PDT 24 |
Apr 21 01:10:37 PM PDT 24 |
889719980 ps |
| T863 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.643755320 |
|
|
Apr 21 01:15:18 PM PDT 24 |
Apr 21 01:17:43 PM PDT 24 |
1519060878 ps |
| T864 |
/workspace/coverage/default/40.sram_ctrl_bijection.2725945733 |
|
|
Apr 21 01:13:30 PM PDT 24 |
Apr 21 01:14:56 PM PDT 24 |
23518486162 ps |
| T865 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3194811096 |
|
|
Apr 21 01:11:11 PM PDT 24 |
Apr 21 01:14:45 PM PDT 24 |
43940712432 ps |
| T866 |
/workspace/coverage/default/6.sram_ctrl_smoke.3164972804 |
|
|
Apr 21 01:09:12 PM PDT 24 |
Apr 21 01:09:17 PM PDT 24 |
244207090 ps |
| T867 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4139600766 |
|
|
Apr 21 01:09:35 PM PDT 24 |
Apr 21 01:09:36 PM PDT 24 |
29566599 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1306785796 |
|
|
Apr 21 01:10:45 PM PDT 24 |
Apr 21 01:11:11 PM PDT 24 |
364389915 ps |
| T869 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3150999405 |
|
|
Apr 21 01:12:06 PM PDT 24 |
Apr 21 01:12:07 PM PDT 24 |
29306799 ps |
| T870 |
/workspace/coverage/default/34.sram_ctrl_executable.1734682976 |
|
|
Apr 21 01:12:30 PM PDT 24 |
Apr 21 01:15:01 PM PDT 24 |
2601357019 ps |
| T871 |
/workspace/coverage/default/44.sram_ctrl_executable.3578865889 |
|
|
Apr 21 01:14:19 PM PDT 24 |
Apr 21 01:27:38 PM PDT 24 |
15265688563 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_executable.558624763 |
|
|
Apr 21 01:14:44 PM PDT 24 |
Apr 21 01:27:23 PM PDT 24 |
3602588796 ps |
| T873 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2842151470 |
|
|
Apr 21 01:13:00 PM PDT 24 |
Apr 21 01:15:20 PM PDT 24 |
52041656259 ps |
| T874 |
/workspace/coverage/default/1.sram_ctrl_regwen.4000690167 |
|
|
Apr 21 01:09:02 PM PDT 24 |
Apr 21 01:20:58 PM PDT 24 |
3356618855 ps |
| T875 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3038788087 |
|
|
Apr 21 01:13:02 PM PDT 24 |
Apr 21 01:18:29 PM PDT 24 |
27208980523 ps |
| T876 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.4020233246 |
|
|
Apr 21 01:11:42 PM PDT 24 |
Apr 21 01:11:43 PM PDT 24 |
85242330 ps |
| T877 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1649247095 |
|
|
Apr 21 01:11:24 PM PDT 24 |
Apr 21 01:12:34 PM PDT 24 |
868893989 ps |
| T878 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.4064721624 |
|
|
Apr 21 01:10:13 PM PDT 24 |
Apr 21 01:10:17 PM PDT 24 |
320081340 ps |
| T879 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3357374265 |
|
|
Apr 21 01:09:05 PM PDT 24 |
Apr 21 01:25:51 PM PDT 24 |
5110847526 ps |
| T880 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3355057096 |
|
|
Apr 21 01:09:12 PM PDT 24 |
Apr 21 01:09:23 PM PDT 24 |
2987224389 ps |
| T881 |
/workspace/coverage/default/45.sram_ctrl_smoke.893116146 |
|
|
Apr 21 01:14:26 PM PDT 24 |
Apr 21 01:14:30 PM PDT 24 |
210185206 ps |
| T882 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1663956461 |
|
|
Apr 21 01:10:02 PM PDT 24 |
Apr 21 01:10:10 PM PDT 24 |
2906027474 ps |
| T883 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.380611046 |
|
|
Apr 21 01:13:09 PM PDT 24 |
Apr 21 01:20:18 PM PDT 24 |
1942687446 ps |
| T884 |
/workspace/coverage/default/8.sram_ctrl_bijection.1678101443 |
|
|
Apr 21 01:09:33 PM PDT 24 |
Apr 21 01:10:01 PM PDT 24 |
1830336523 ps |
| T885 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1533477618 |
|
|
Apr 21 01:11:16 PM PDT 24 |
Apr 21 01:11:20 PM PDT 24 |
614053107 ps |
| T886 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1756444736 |
|
|
Apr 21 01:10:22 PM PDT 24 |
Apr 21 01:10:57 PM PDT 24 |
115458006 ps |
| T887 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3708685188 |
|
|
Apr 21 01:12:31 PM PDT 24 |
Apr 21 01:12:32 PM PDT 24 |
83174389 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2795186731 |
|
|
Apr 21 01:14:05 PM PDT 24 |
Apr 21 01:18:12 PM PDT 24 |
1096761835 ps |
| T889 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1881274277 |
|
|
Apr 21 01:09:47 PM PDT 24 |
Apr 21 01:22:11 PM PDT 24 |
25798871122 ps |
| T890 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2621564821 |
|
|
Apr 21 01:10:23 PM PDT 24 |
Apr 21 01:13:46 PM PDT 24 |
4553215889 ps |
| T891 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1916172445 |
|
|
Apr 21 01:09:16 PM PDT 24 |
Apr 21 01:13:18 PM PDT 24 |
2227191634 ps |
| T892 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.59211021 |
|
|
Apr 21 01:11:57 PM PDT 24 |
Apr 21 01:13:08 PM PDT 24 |
501851063 ps |
| T893 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1031567136 |
|
|
Apr 21 01:09:04 PM PDT 24 |
Apr 21 01:10:23 PM PDT 24 |
140348156 ps |
| T894 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2786676044 |
|
|
Apr 21 01:09:09 PM PDT 24 |
Apr 21 01:19:54 PM PDT 24 |
2921313165 ps |
| T895 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3869144159 |
|
|
Apr 21 01:09:04 PM PDT 24 |
Apr 21 01:09:13 PM PDT 24 |
1153523804 ps |
| T896 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.93487281 |
|
|
Apr 21 01:12:12 PM PDT 24 |
Apr 21 01:12:14 PM PDT 24 |
310187504 ps |
| T897 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1407797168 |
|
|
Apr 21 01:12:44 PM PDT 24 |
Apr 21 01:12:49 PM PDT 24 |
61732572 ps |
| T898 |
/workspace/coverage/default/31.sram_ctrl_bijection.3826248229 |
|
|
Apr 21 01:11:56 PM PDT 24 |
Apr 21 01:12:34 PM PDT 24 |
1832740420 ps |
| T899 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.255445889 |
|
|
Apr 21 01:14:57 PM PDT 24 |
Apr 21 01:15:00 PM PDT 24 |
102275658 ps |
| T900 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2565287199 |
|
|
Apr 21 01:11:39 PM PDT 24 |
Apr 21 01:11:44 PM PDT 24 |
516220697 ps |
| T901 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1190707853 |
|
|
Apr 21 01:10:44 PM PDT 24 |
Apr 21 01:10:51 PM PDT 24 |
190858267 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4129785196 |
|
|
Apr 21 01:09:12 PM PDT 24 |
Apr 21 01:10:02 PM PDT 24 |
1773034920 ps |
| T903 |
/workspace/coverage/default/12.sram_ctrl_partial_access.864853043 |
|
|
Apr 21 01:09:48 PM PDT 24 |
Apr 21 01:09:55 PM PDT 24 |
507452051 ps |
| T904 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1438597399 |
|
|
Apr 21 01:09:25 PM PDT 24 |
Apr 21 01:09:31 PM PDT 24 |
342350827 ps |
| T905 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3979301075 |
|
|
Apr 21 01:14:43 PM PDT 24 |
Apr 21 01:14:51 PM PDT 24 |
3328338065 ps |
| T906 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1244046073 |
|
|
Apr 21 01:10:46 PM PDT 24 |
Apr 21 01:10:51 PM PDT 24 |
285301806 ps |
| T907 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2996262918 |
|
|
Apr 21 01:09:00 PM PDT 24 |
Apr 21 01:09:01 PM PDT 24 |
32938521 ps |
| T908 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2893096682 |
|
|
Apr 21 01:10:19 PM PDT 24 |
Apr 21 01:10:19 PM PDT 24 |
34838335 ps |
| T909 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.394711048 |
|
|
Apr 21 01:13:04 PM PDT 24 |
Apr 21 01:13:14 PM PDT 24 |
1327373139 ps |
| T910 |
/workspace/coverage/default/35.sram_ctrl_smoke.4194404689 |
|
|
Apr 21 01:12:34 PM PDT 24 |
Apr 21 01:12:45 PM PDT 24 |
160248316 ps |
| T911 |
/workspace/coverage/default/7.sram_ctrl_executable.3285856512 |
|
|
Apr 21 01:09:20 PM PDT 24 |
Apr 21 01:14:54 PM PDT 24 |
1818625235 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.185125083 |
|
|
Apr 21 01:15:23 PM PDT 24 |
Apr 21 01:15:32 PM PDT 24 |
940142436 ps |
| T913 |
/workspace/coverage/default/15.sram_ctrl_executable.3075416792 |
|
|
Apr 21 01:10:03 PM PDT 24 |
Apr 21 01:32:52 PM PDT 24 |
83658020652 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3740342378 |
|
|
Apr 21 01:11:59 PM PDT 24 |
Apr 21 01:19:49 PM PDT 24 |
2001726095 ps |
| T915 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.350436282 |
|
|
Apr 21 01:10:03 PM PDT 24 |
Apr 21 01:10:20 PM PDT 24 |
602034818 ps |
| T916 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1598069862 |
|
|
Apr 21 01:11:02 PM PDT 24 |
Apr 21 01:11:08 PM PDT 24 |
361868223 ps |
| T917 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.941733997 |
|
|
Apr 21 01:13:34 PM PDT 24 |
Apr 21 01:16:58 PM PDT 24 |
46179907722 ps |
| T918 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.3377514998 |
|
|
Apr 21 01:11:38 PM PDT 24 |
Apr 21 01:23:21 PM PDT 24 |
5011098362 ps |
| T919 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.563033771 |
|
|
Apr 21 01:09:14 PM PDT 24 |
Apr 21 01:09:15 PM PDT 24 |
27337675 ps |
| T920 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3843356338 |
|
|
Apr 21 01:09:42 PM PDT 24 |
Apr 21 01:09:44 PM PDT 24 |
181077531 ps |
| T921 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3069119975 |
|
|
Apr 21 01:11:28 PM PDT 24 |
Apr 21 01:11:31 PM PDT 24 |
323647890 ps |
| T922 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3731519408 |
|
|
Apr 21 01:11:04 PM PDT 24 |
Apr 21 01:15:41 PM PDT 24 |
1368092846 ps |
| T923 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3157983003 |
|
|
Apr 21 01:09:23 PM PDT 24 |
Apr 21 01:09:24 PM PDT 24 |
81144507 ps |
| T924 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1093002150 |
|
|
Apr 21 01:13:50 PM PDT 24 |
Apr 21 01:13:54 PM PDT 24 |
247517193 ps |
| T925 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3207580018 |
|
|
Apr 21 01:12:17 PM PDT 24 |
Apr 21 01:16:44 PM PDT 24 |
2589600634 ps |
| T926 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.273605872 |
|
|
Apr 21 01:10:25 PM PDT 24 |
Apr 21 01:10:25 PM PDT 24 |
75432976 ps |
| T927 |
/workspace/coverage/default/33.sram_ctrl_partial_access.410607265 |
|
|
Apr 21 01:12:16 PM PDT 24 |
Apr 21 01:12:24 PM PDT 24 |
161305489 ps |
| T928 |
/workspace/coverage/default/10.sram_ctrl_smoke.410493431 |
|
|
Apr 21 01:09:39 PM PDT 24 |
Apr 21 01:09:40 PM PDT 24 |
87854339 ps |
| T929 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4271627851 |
|
|
Apr 21 01:12:59 PM PDT 24 |
Apr 21 01:14:02 PM PDT 24 |
580728383 ps |
| T930 |
/workspace/coverage/default/25.sram_ctrl_alert_test.475421364 |
|
|
Apr 21 01:11:12 PM PDT 24 |
Apr 21 01:11:12 PM PDT 24 |
11436490 ps |
| T931 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.123051269 |
|
|
Apr 21 01:13:36 PM PDT 24 |
Apr 21 01:24:22 PM PDT 24 |
9479097493 ps |
| T932 |
/workspace/coverage/default/27.sram_ctrl_smoke.2488738980 |
|
|
Apr 21 01:11:19 PM PDT 24 |
Apr 21 01:12:47 PM PDT 24 |
2201817638 ps |
| T933 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3985856304 |
|
|
Apr 21 01:09:08 PM PDT 24 |
Apr 21 01:09:34 PM PDT 24 |
174814877 ps |
| T934 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3287397813 |
|
|
Apr 21 01:12:08 PM PDT 24 |
Apr 21 01:15:04 PM PDT 24 |
1951924361 ps |
| T935 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2348335174 |
|
|
Apr 21 01:10:58 PM PDT 24 |
Apr 21 01:11:04 PM PDT 24 |
650823001 ps |
| T936 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4187431389 |
|
|
Apr 21 01:10:43 PM PDT 24 |
Apr 21 01:10:47 PM PDT 24 |
298683457 ps |
| T937 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.3570094792 |
|
|
Apr 21 01:10:26 PM PDT 24 |
Apr 21 01:10:36 PM PDT 24 |
2222952971 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3581353599 |
|
|
Apr 21 12:43:42 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
682474158 ps |
| T938 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.949875310 |
|
|
Apr 21 12:43:47 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
29620504 ps |
| T939 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2408713021 |
|
|
Apr 21 12:43:41 PM PDT 24 |
Apr 21 12:43:44 PM PDT 24 |
36878909 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2465179986 |
|
|
Apr 21 12:43:38 PM PDT 24 |
Apr 21 12:43:39 PM PDT 24 |
180821852 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1541800358 |
|
|
Apr 21 12:43:37 PM PDT 24 |
Apr 21 12:43:38 PM PDT 24 |
25489641 ps |
| T95 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2496532792 |
|
|
Apr 21 12:43:43 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
161580825 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.769675822 |
|
|
Apr 21 12:43:43 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
41844315 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2614030905 |
|
|
Apr 21 12:43:42 PM PDT 24 |
Apr 21 12:43:44 PM PDT 24 |
27264688 ps |
| T940 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4173401602 |
|
|
Apr 21 12:43:43 PM PDT 24 |
Apr 21 12:43:47 PM PDT 24 |
37775546 ps |
| T941 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1115354926 |
|
|
Apr 21 12:43:56 PM PDT 24 |
Apr 21 12:43:59 PM PDT 24 |
197870187 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3953743942 |
|
|
Apr 21 12:43:40 PM PDT 24 |
Apr 21 12:43:43 PM PDT 24 |
83076788 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3627467084 |
|
|
Apr 21 12:43:43 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
27888298 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1956225028 |
|
|
Apr 21 12:43:50 PM PDT 24 |
Apr 21 12:43:54 PM PDT 24 |
207001818 ps |
| T71 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2848597346 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
44152552 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1100329890 |
|
|
Apr 21 12:43:39 PM PDT 24 |
Apr 21 12:43:40 PM PDT 24 |
22050301 ps |
| T106 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3723381841 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
12373491 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2274716773 |
|
|
Apr 21 12:43:41 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
69744669 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.155971348 |
|
|
Apr 21 12:43:53 PM PDT 24 |
Apr 21 12:43:54 PM PDT 24 |
100509050 ps |
| T107 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3785225653 |
|
|
Apr 21 12:43:42 PM PDT 24 |
Apr 21 12:43:44 PM PDT 24 |
429869805 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.742808279 |
|
|
Apr 21 12:43:50 PM PDT 24 |
Apr 21 12:43:52 PM PDT 24 |
139305309 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.34133544 |
|
|
Apr 21 12:43:40 PM PDT 24 |
Apr 21 12:43:44 PM PDT 24 |
182582677 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1765686138 |
|
|
Apr 21 12:43:43 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
568373162 ps |
| T74 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3268143038 |
|
|
Apr 21 12:43:55 PM PDT 24 |
Apr 21 12:43:56 PM PDT 24 |
127011003 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1859795305 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
26866306 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.803242435 |
|
|
Apr 21 12:43:39 PM PDT 24 |
Apr 21 12:43:42 PM PDT 24 |
988550013 ps |
| T77 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2735663222 |
|
|
Apr 21 12:43:48 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
15045261 ps |
| T78 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.129829741 |
|
|
Apr 21 12:43:30 PM PDT 24 |
Apr 21 12:43:34 PM PDT 24 |
4700267488 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.541223166 |
|
|
Apr 21 12:43:33 PM PDT 24 |
Apr 21 12:43:36 PM PDT 24 |
122825037 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2000022255 |
|
|
Apr 21 12:44:06 PM PDT 24 |
Apr 21 12:44:09 PM PDT 24 |
407094229 ps |
| T947 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.107984902 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:52 PM PDT 24 |
973336720 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3531154621 |
|
|
Apr 21 12:44:06 PM PDT 24 |
Apr 21 12:44:09 PM PDT 24 |
882768044 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3343181035 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
31324741 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.658912275 |
|
|
Apr 21 12:44:00 PM PDT 24 |
Apr 21 12:44:03 PM PDT 24 |
248960176 ps |
| T950 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3603986870 |
|
|
Apr 21 12:43:48 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
41427410 ps |
| T951 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.183552821 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
145798909 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3147486247 |
|
|
Apr 21 12:43:56 PM PDT 24 |
Apr 21 12:43:58 PM PDT 24 |
914319045 ps |
| T109 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1859177866 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
366302709 ps |
| T952 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3616939230 |
|
|
Apr 21 12:43:53 PM PDT 24 |
Apr 21 12:43:55 PM PDT 24 |
30060629 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.876552027 |
|
|
Apr 21 12:43:48 PM PDT 24 |
Apr 21 12:43:54 PM PDT 24 |
581295812 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3801825598 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
289404828 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2474292896 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
19886240 ps |
| T123 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2834006684 |
|
|
Apr 21 12:43:36 PM PDT 24 |
Apr 21 12:43:39 PM PDT 24 |
181976743 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3655280029 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:48 PM PDT 24 |
78497567 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2214355567 |
|
|
Apr 21 12:44:07 PM PDT 24 |
Apr 21 12:44:10 PM PDT 24 |
45267766 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3273954401 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:57 PM PDT 24 |
148429715 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.226154006 |
|
|
Apr 21 12:43:40 PM PDT 24 |
Apr 21 12:43:42 PM PDT 24 |
85381919 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2626857730 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:49 PM PDT 24 |
351753634 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.215033077 |
|
|
Apr 21 12:43:44 PM PDT 24 |
Apr 21 12:43:47 PM PDT 24 |
32506920 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4010097659 |
|
|
Apr 21 12:43:50 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
16259286 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.830652269 |
|
|
Apr 21 12:43:48 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
292526702 ps |
| T962 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1749260709 |
|
|
Apr 21 12:43:49 PM PDT 24 |
Apr 21 12:43:55 PM PDT 24 |
110817779 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2869232226 |
|
|
Apr 21 12:43:42 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
2219517170 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3662947361 |
|
|
Apr 21 12:43:27 PM PDT 24 |
Apr 21 12:43:29 PM PDT 24 |
517355116 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4033945507 |
|
|
Apr 21 12:44:09 PM PDT 24 |
Apr 21 12:44:11 PM PDT 24 |
15389513 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2297317701 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
130150403 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4048575469 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
246506693 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1100006544 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:49 PM PDT 24 |
125918968 ps |
| T967 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1606706028 |
|
|
Apr 21 12:43:40 PM PDT 24 |
Apr 21 12:43:42 PM PDT 24 |
36856105 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2293989787 |
|
|
Apr 21 12:43:31 PM PDT 24 |
Apr 21 12:43:32 PM PDT 24 |
44338902 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1132234135 |
|
|
Apr 21 12:43:54 PM PDT 24 |
Apr 21 12:43:56 PM PDT 24 |
45404914 ps |
| T120 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.563233444 |
|
|
Apr 21 12:43:50 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
78952758 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.789157582 |
|
|
Apr 21 12:43:36 PM PDT 24 |
Apr 21 12:43:39 PM PDT 24 |
247427929 ps |
| T971 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1192188064 |
|
|
Apr 21 12:43:42 PM PDT 24 |
Apr 21 12:43:43 PM PDT 24 |
63989030 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.812557141 |
|
|
Apr 21 12:43:34 PM PDT 24 |
Apr 21 12:43:38 PM PDT 24 |
228476628 ps |
| T124 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3168337441 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
283886322 ps |
| T82 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2323794785 |
|
|
Apr 21 12:43:53 PM PDT 24 |
Apr 21 12:43:55 PM PDT 24 |
281667475 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3915723893 |
|
|
Apr 21 12:43:35 PM PDT 24 |
Apr 21 12:43:36 PM PDT 24 |
21047554 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2731626679 |
|
|
Apr 21 12:43:41 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
61256312 ps |
| T92 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3991258990 |
|
|
Apr 21 12:43:36 PM PDT 24 |
Apr 21 12:43:38 PM PDT 24 |
21831231 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3407426190 |
|
|
Apr 21 12:43:35 PM PDT 24 |
Apr 21 12:43:37 PM PDT 24 |
92011716 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3884678261 |
|
|
Apr 21 12:43:59 PM PDT 24 |
Apr 21 12:44:00 PM PDT 24 |
41783841 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2065642605 |
|
|
Apr 21 12:43:42 PM PDT 24 |
Apr 21 12:43:49 PM PDT 24 |
1374280004 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3973087958 |
|
|
Apr 21 12:43:53 PM PDT 24 |
Apr 21 12:43:55 PM PDT 24 |
49995641 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2222157960 |
|
|
Apr 21 12:43:55 PM PDT 24 |
Apr 21 12:43:59 PM PDT 24 |
346983608 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2415866175 |
|
|
Apr 21 12:43:51 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
14258222 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3242727937 |
|
|
Apr 21 12:43:50 PM PDT 24 |
Apr 21 12:43:55 PM PDT 24 |
1395974867 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4015846629 |
|
|
Apr 21 12:43:55 PM PDT 24 |
Apr 21 12:43:57 PM PDT 24 |
16098118 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2512396675 |
|
|
Apr 21 12:43:44 PM PDT 24 |
Apr 21 12:43:49 PM PDT 24 |
758510345 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2535176173 |
|
|
Apr 21 12:43:51 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
68914504 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2744837510 |
|
|
Apr 21 12:43:57 PM PDT 24 |
Apr 21 12:43:59 PM PDT 24 |
46640652 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3971094940 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:52 PM PDT 24 |
730612862 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2892443599 |
|
|
Apr 21 12:43:47 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
57095991 ps |
| T985 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.732009753 |
|
|
Apr 21 12:43:48 PM PDT 24 |
Apr 21 12:43:52 PM PDT 24 |
87139367 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1083186380 |
|
|
Apr 21 12:44:01 PM PDT 24 |
Apr 21 12:44:03 PM PDT 24 |
12867906 ps |
| T987 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2749807681 |
|
|
Apr 21 12:43:50 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
412989695 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.583176697 |
|
|
Apr 21 12:43:45 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
1540160489 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1937688235 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
325846415 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1895085180 |
|
|
Apr 21 12:43:37 PM PDT 24 |
Apr 21 12:43:39 PM PDT 24 |
77710027 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2294883421 |
|
|
Apr 21 12:43:43 PM PDT 24 |
Apr 21 12:43:45 PM PDT 24 |
16389391 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1609575022 |
|
|
Apr 21 12:43:47 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
25133324 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2571833057 |
|
|
Apr 21 12:44:03 PM PDT 24 |
Apr 21 12:44:07 PM PDT 24 |
861984755 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2581563744 |
|
|
Apr 21 12:43:44 PM PDT 24 |
Apr 21 12:43:47 PM PDT 24 |
37458394 ps |
| T992 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1309320151 |
|
|
Apr 21 12:43:47 PM PDT 24 |
Apr 21 12:43:50 PM PDT 24 |
25146047 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1299996877 |
|
|
Apr 21 12:44:00 PM PDT 24 |
Apr 21 12:44:04 PM PDT 24 |
77839297 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3970774657 |
|
|
Apr 21 12:43:48 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
45051270 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2734096941 |
|
|
Apr 21 12:43:36 PM PDT 24 |
Apr 21 12:43:39 PM PDT 24 |
688104806 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1591592196 |
|
|
Apr 21 12:43:49 PM PDT 24 |
Apr 21 12:43:53 PM PDT 24 |
203302445 ps |
| T122 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3531298443 |
|
|
Apr 21 12:43:52 PM PDT 24 |
Apr 21 12:43:55 PM PDT 24 |
390611707 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2154119379 |
|
|
Apr 21 12:43:59 PM PDT 24 |
Apr 21 12:44:02 PM PDT 24 |
449549681 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.635785326 |
|
|
Apr 21 12:43:57 PM PDT 24 |
Apr 21 12:44:01 PM PDT 24 |
399844318 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1926739960 |
|
|
Apr 21 12:43:37 PM PDT 24 |
Apr 21 12:43:38 PM PDT 24 |
15624550 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.442640366 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:51 PM PDT 24 |
236731537 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3496965628 |
|
|
Apr 21 12:43:44 PM PDT 24 |
Apr 21 12:43:46 PM PDT 24 |
422187849 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3189120215 |
|
|
Apr 21 12:43:33 PM PDT 24 |
Apr 21 12:43:34 PM PDT 24 |
53594365 ps |
| T1002 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3731320424 |
|
|
Apr 21 12:43:56 PM PDT 24 |
Apr 21 12:43:57 PM PDT 24 |
93470550 ps |
| T1003 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.637697803 |
|
|
Apr 21 12:43:46 PM PDT 24 |
Apr 21 12:43:52 PM PDT 24 |
641284681 ps |