Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	144959856	1			T1	3898		T2	295416		T3	2928
instr_valid_dis	111576789	1			T1	3898		T2	274850		T3	2928
instr_en	23239709	1			T2	20566		T11	560364		T22	15262

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11248617	1			T2	25152		T11	280796		T22	15318
sram_ifetch_valid_disable	111457238	1			T1	3898		T2	154484		T3	2928
sram_ifetch_enable	22254001	1			T2	115780		T11	611792		T54	159322

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	144959856	1			T1	3898		T2	295416		T3	2928
hw_debug_en_valid_off	112256208	1			T1	3898		T2	111390		T3	2928
hw_debug_en_on	22135280	1			T2	126126		T11	543362		T22	15318

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111457238	1			T1	3898		T2	154484		T3	2928
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97862592	1			T1	3898		T2	154484		T3	2928
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9274776	1			T11	354728		T54	129070		T72	44548
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4449416	1			T2	17188		T11	133664		T54	58660
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1862972	1			T2	17188		T11	71004		T23	854
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1718454	1			T11	62660		T54	58660		T6	20764
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4696263	1			T2	7964		T11	93760		T22	15318
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1907067	1			T2	7964		T11	21740		T22	56
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2204422	1			T11	29684		T22	15262		T54	11232
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9393864	1			T2	118162		T11	250286		T54	14238
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4089442	1			T2	118162		T11	17072		T72	13040
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3562852	1			T11	204412		T54	14238		T6	55422

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9305175	1			T2	20566		T11	100860		T54	159322
lc_exec_en	8045153	1			T11	199316		T54	8608		T72	119212
valid_exec_dis	106704608	1			T1	3898		T2	95214		T3	2928
invalid_exec_dis	33502618	1			T2	140932		T11	892588		T22	15318