Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42470573	1			T1	106		T2	53859		T3	97
triple_byte_access	2439963	1			T1	222		T2	1032		T3	2
halfword_access	3663414	1			T1	407		T2	1606		T3	3
byte_access	4892418	1			T1	789		T2	2134		T3	2
zero_access	1231446	1			T1	425		T2	593		T3	1

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27299013

1

T1

851

T2

29500

T3

47

auto[1]

27398801

1

T1

1098

T2

29724

T3

58

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21190118	1			T1	8		T2	26845		T3	41
auto[0]	triple_byte_access	1216448	1			T1	27		T2	497		T3	2
auto[0]	halfword_access	1828744	1			T1	110		T2	776		T3	2
auto[0]	byte_access	2444969	1			T1	365		T2	1082		T3	2
auto[0]	zero_access	618734	1			T1	341		T2	300		T4	333
auto[1]	word_access	21280455	1			T1	98		T2	27014		T3	56
auto[1]	triple_byte_access	1223515	1			T1	195		T2	535		T4	217
auto[1]	halfword_access	1834670	1			T1	297		T2	830		T3	1
auto[1]	byte_access	2447449	1			T1	424		T2	1052		T4	402
auto[1]	zero_access	612712	1			T1	84		T2	293		T3	1