| T795 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3903624340 |
|
|
May 02 03:20:11 PM PDT 24 |
May 02 03:20:15 PM PDT 24 |
164379342 ps |
| T796 |
/workspace/coverage/default/21.sram_ctrl_smoke.3331998798 |
|
|
May 02 03:17:04 PM PDT 24 |
May 02 03:17:07 PM PDT 24 |
179068060 ps |
| T797 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2175291742 |
|
|
May 02 03:17:04 PM PDT 24 |
May 02 03:22:42 PM PDT 24 |
4987236362 ps |
| T798 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1953153300 |
|
|
May 02 03:20:26 PM PDT 24 |
May 02 03:21:45 PM PDT 24 |
2593637456 ps |
| T799 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3573226213 |
|
|
May 02 03:22:53 PM PDT 24 |
May 02 03:22:59 PM PDT 24 |
178652538 ps |
| T800 |
/workspace/coverage/default/29.sram_ctrl_smoke.1857427047 |
|
|
May 02 03:19:08 PM PDT 24 |
May 02 03:19:28 PM PDT 24 |
68789479 ps |
| T801 |
/workspace/coverage/default/25.sram_ctrl_smoke.1493926098 |
|
|
May 02 03:18:03 PM PDT 24 |
May 02 03:18:15 PM PDT 24 |
1336012898 ps |
| T802 |
/workspace/coverage/default/14.sram_ctrl_bijection.943544200 |
|
|
May 02 03:15:16 PM PDT 24 |
May 02 03:15:46 PM PDT 24 |
487746952 ps |
| T803 |
/workspace/coverage/default/24.sram_ctrl_alert_test.1881912291 |
|
|
May 02 03:17:58 PM PDT 24 |
May 02 03:18:00 PM PDT 24 |
17711105 ps |
| T804 |
/workspace/coverage/default/32.sram_ctrl_bijection.1755164165 |
|
|
May 02 03:19:55 PM PDT 24 |
May 02 03:21:05 PM PDT 24 |
38868743130 ps |
| T805 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1753713390 |
|
|
May 02 03:12:09 PM PDT 24 |
May 02 03:12:13 PM PDT 24 |
155755674 ps |
| T806 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.972531209 |
|
|
May 02 03:17:08 PM PDT 24 |
May 02 03:17:14 PM PDT 24 |
338124768 ps |
| T807 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4279021247 |
|
|
May 02 03:13:01 PM PDT 24 |
May 02 03:13:16 PM PDT 24 |
323571138 ps |
| T808 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3553395196 |
|
|
May 02 03:18:38 PM PDT 24 |
May 02 03:24:03 PM PDT 24 |
11621101413 ps |
| T809 |
/workspace/coverage/default/3.sram_ctrl_executable.3814457970 |
|
|
May 02 03:12:36 PM PDT 24 |
May 02 03:18:02 PM PDT 24 |
6404810282 ps |
| T810 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3616364345 |
|
|
May 02 03:16:30 PM PDT 24 |
May 02 03:16:33 PM PDT 24 |
159098955 ps |
| T811 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2287437458 |
|
|
May 02 03:23:46 PM PDT 24 |
May 02 03:23:47 PM PDT 24 |
14912417 ps |
| T812 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1249755982 |
|
|
May 02 03:22:36 PM PDT 24 |
May 02 03:22:39 PM PDT 24 |
48122422 ps |
| T813 |
/workspace/coverage/default/35.sram_ctrl_regwen.2699754556 |
|
|
May 02 03:20:47 PM PDT 24 |
May 02 03:34:46 PM PDT 24 |
10119955399 ps |
| T814 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.415526862 |
|
|
May 02 03:13:24 PM PDT 24 |
May 02 03:41:36 PM PDT 24 |
55610022566 ps |
| T815 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2073116533 |
|
|
May 02 03:21:38 PM PDT 24 |
May 02 03:22:27 PM PDT 24 |
437693559 ps |
| T816 |
/workspace/coverage/default/5.sram_ctrl_bijection.1524428895 |
|
|
May 02 03:12:57 PM PDT 24 |
May 02 03:13:47 PM PDT 24 |
1615981830 ps |
| T817 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3773403489 |
|
|
May 02 03:18:46 PM PDT 24 |
May 02 03:18:52 PM PDT 24 |
288990023 ps |
| T818 |
/workspace/coverage/default/46.sram_ctrl_regwen.2500322594 |
|
|
May 02 03:23:46 PM PDT 24 |
May 02 03:41:10 PM PDT 24 |
6764406388 ps |
| T819 |
/workspace/coverage/default/2.sram_ctrl_regwen.2913607635 |
|
|
May 02 03:12:24 PM PDT 24 |
May 02 03:20:37 PM PDT 24 |
5905893925 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3507165022 |
|
|
May 02 03:12:29 PM PDT 24 |
May 02 03:12:32 PM PDT 24 |
106284514 ps |
| T821 |
/workspace/coverage/default/23.sram_ctrl_bijection.2413112734 |
|
|
May 02 03:17:26 PM PDT 24 |
May 02 03:18:06 PM PDT 24 |
2487566740 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.121717070 |
|
|
May 02 03:18:15 PM PDT 24 |
May 02 03:18:21 PM PDT 24 |
182129695 ps |
| T823 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.668226141 |
|
|
May 02 03:20:03 PM PDT 24 |
May 02 03:20:56 PM PDT 24 |
1031490463 ps |
| T824 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.527504039 |
|
|
May 02 03:12:50 PM PDT 24 |
May 02 03:12:58 PM PDT 24 |
2019573203 ps |
| T825 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2409829043 |
|
|
May 02 03:21:50 PM PDT 24 |
May 02 03:24:33 PM PDT 24 |
679997238 ps |
| T826 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1664292815 |
|
|
May 02 03:22:43 PM PDT 24 |
May 02 03:25:24 PM PDT 24 |
6916234803 ps |
| T827 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.435043023 |
|
|
May 02 03:21:54 PM PDT 24 |
May 02 03:28:55 PM PDT 24 |
59501823632 ps |
| T828 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1057817446 |
|
|
May 02 03:21:52 PM PDT 24 |
May 02 03:39:42 PM PDT 24 |
3437330151 ps |
| T829 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3415881318 |
|
|
May 02 03:22:34 PM PDT 24 |
May 02 04:21:02 PM PDT 24 |
11048044930 ps |
| T830 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.4258226787 |
|
|
May 02 03:16:41 PM PDT 24 |
May 02 03:22:28 PM PDT 24 |
28183623314 ps |
| T831 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1321160513 |
|
|
May 02 03:20:11 PM PDT 24 |
May 02 04:00:14 PM PDT 24 |
100376855815 ps |
| T832 |
/workspace/coverage/default/22.sram_ctrl_alert_test.625799723 |
|
|
May 02 03:17:26 PM PDT 24 |
May 02 03:17:28 PM PDT 24 |
40991958 ps |
| T833 |
/workspace/coverage/default/21.sram_ctrl_partial_access.18584016 |
|
|
May 02 03:17:04 PM PDT 24 |
May 02 03:17:14 PM PDT 24 |
262241828 ps |
| T834 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1997124556 |
|
|
May 02 03:12:56 PM PDT 24 |
May 02 03:16:54 PM PDT 24 |
797802224 ps |
| T835 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3477355650 |
|
|
May 02 03:22:43 PM PDT 24 |
May 02 03:25:20 PM PDT 24 |
13249485036 ps |
| T836 |
/workspace/coverage/default/12.sram_ctrl_smoke.2885021606 |
|
|
May 02 03:14:44 PM PDT 24 |
May 02 03:14:49 PM PDT 24 |
124458519 ps |
| T837 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3990003365 |
|
|
May 02 03:23:40 PM PDT 24 |
May 02 03:29:15 PM PDT 24 |
13638020975 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.925545728 |
|
|
May 02 03:18:38 PM PDT 24 |
May 02 03:18:41 PM PDT 24 |
39865713 ps |
| T31 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.153706110 |
|
|
May 02 03:12:56 PM PDT 24 |
May 02 03:12:59 PM PDT 24 |
563905637 ps |
| T839 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1208263730 |
|
|
May 02 03:24:21 PM PDT 24 |
May 02 03:24:27 PM PDT 24 |
374352851 ps |
| T840 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3135332035 |
|
|
May 02 03:21:50 PM PDT 24 |
May 02 03:21:59 PM PDT 24 |
150056227 ps |
| T841 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1503411388 |
|
|
May 02 03:18:02 PM PDT 24 |
May 02 03:35:17 PM PDT 24 |
61492886999 ps |
| T842 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3117987157 |
|
|
May 02 03:14:47 PM PDT 24 |
May 02 03:30:24 PM PDT 24 |
12019853077 ps |
| T843 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2450594615 |
|
|
May 02 03:13:16 PM PDT 24 |
May 02 03:14:32 PM PDT 24 |
520319793 ps |
| T844 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3700817411 |
|
|
May 02 03:18:47 PM PDT 24 |
May 02 03:18:49 PM PDT 24 |
77941258 ps |
| T845 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1667157648 |
|
|
May 02 03:12:43 PM PDT 24 |
May 02 03:32:11 PM PDT 24 |
7156863491 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.754194313 |
|
|
May 02 03:13:59 PM PDT 24 |
May 02 03:21:44 PM PDT 24 |
18203106746 ps |
| T847 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1293791649 |
|
|
May 02 03:12:54 PM PDT 24 |
May 02 03:28:24 PM PDT 24 |
7337031852 ps |
| T848 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1304880911 |
|
|
May 02 03:23:46 PM PDT 24 |
May 02 03:23:52 PM PDT 24 |
304359359 ps |
| T849 |
/workspace/coverage/default/24.sram_ctrl_bijection.3920453256 |
|
|
May 02 03:17:51 PM PDT 24 |
May 02 03:18:10 PM PDT 24 |
1105637486 ps |
| T850 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1281917263 |
|
|
May 02 03:15:50 PM PDT 24 |
May 02 03:16:03 PM PDT 24 |
1275666365 ps |
| T851 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3361491360 |
|
|
May 02 03:22:34 PM PDT 24 |
May 02 03:22:35 PM PDT 24 |
19416857 ps |
| T852 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.249023315 |
|
|
May 02 03:24:23 PM PDT 24 |
May 02 03:32:10 PM PDT 24 |
48907451476 ps |
| T853 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.2221833603 |
|
|
May 02 03:19:02 PM PDT 24 |
May 02 03:19:07 PM PDT 24 |
66387215 ps |
| T854 |
/workspace/coverage/default/21.sram_ctrl_regwen.3292265937 |
|
|
May 02 03:17:11 PM PDT 24 |
May 02 03:33:02 PM PDT 24 |
17153142786 ps |
| T855 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1484735766 |
|
|
May 02 03:17:24 PM PDT 24 |
May 02 03:21:17 PM PDT 24 |
1331380660 ps |
| T856 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1742221705 |
|
|
May 02 03:14:25 PM PDT 24 |
May 02 03:48:55 PM PDT 24 |
81640085754 ps |
| T857 |
/workspace/coverage/default/12.sram_ctrl_alert_test.474060498 |
|
|
May 02 03:14:56 PM PDT 24 |
May 02 03:14:57 PM PDT 24 |
13994735 ps |
| T858 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1963523815 |
|
|
May 02 03:13:16 PM PDT 24 |
May 02 03:13:27 PM PDT 24 |
5969363763 ps |
| T859 |
/workspace/coverage/default/6.sram_ctrl_regwen.1199043689 |
|
|
May 02 03:13:15 PM PDT 24 |
May 02 03:34:06 PM PDT 24 |
3293281557 ps |
| T860 |
/workspace/coverage/default/26.sram_ctrl_bijection.2591523395 |
|
|
May 02 03:18:18 PM PDT 24 |
May 02 03:19:12 PM PDT 24 |
1669905236 ps |
| T861 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.697507586 |
|
|
May 02 03:22:29 PM PDT 24 |
May 02 03:24:50 PM PDT 24 |
649045074 ps |
| T862 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1517181822 |
|
|
May 02 03:23:40 PM PDT 24 |
May 02 03:39:18 PM PDT 24 |
3196308154 ps |
| T863 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1303532677 |
|
|
May 02 03:20:56 PM PDT 24 |
May 02 03:25:01 PM PDT 24 |
37466033893 ps |
| T864 |
/workspace/coverage/default/25.sram_ctrl_partial_access.198775108 |
|
|
May 02 03:18:02 PM PDT 24 |
May 02 03:18:06 PM PDT 24 |
55032113 ps |
| T865 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2285781489 |
|
|
May 02 03:18:03 PM PDT 24 |
May 02 03:24:51 PM PDT 24 |
56582486989 ps |
| T866 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2553832877 |
|
|
May 02 03:13:18 PM PDT 24 |
May 02 03:32:28 PM PDT 24 |
9703686581 ps |
| T867 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1291061437 |
|
|
May 02 03:21:31 PM PDT 24 |
May 02 03:21:35 PM PDT 24 |
185315321 ps |
| T868 |
/workspace/coverage/default/24.sram_ctrl_smoke.3056115217 |
|
|
May 02 03:17:42 PM PDT 24 |
May 02 03:19:35 PM PDT 24 |
585973127 ps |
| T869 |
/workspace/coverage/default/24.sram_ctrl_regwen.3739388438 |
|
|
May 02 03:17:50 PM PDT 24 |
May 02 03:47:51 PM PDT 24 |
38609557323 ps |
| T870 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2292465385 |
|
|
May 02 03:18:45 PM PDT 24 |
May 02 03:20:19 PM PDT 24 |
4490261832 ps |
| T871 |
/workspace/coverage/default/44.sram_ctrl_bijection.2355536096 |
|
|
May 02 03:23:09 PM PDT 24 |
May 02 03:23:25 PM PDT 24 |
471222533 ps |
| T872 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3539254656 |
|
|
May 02 03:21:03 PM PDT 24 |
May 02 03:22:51 PM PDT 24 |
491228937 ps |
| T873 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2889839058 |
|
|
May 02 03:12:29 PM PDT 24 |
May 02 03:12:39 PM PDT 24 |
87330771 ps |
| T874 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1842496994 |
|
|
May 02 03:23:06 PM PDT 24 |
May 02 03:23:12 PM PDT 24 |
427733222 ps |
| T875 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1875846084 |
|
|
May 02 03:15:33 PM PDT 24 |
May 02 03:15:38 PM PDT 24 |
991738588 ps |
| T876 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3218931312 |
|
|
May 02 03:15:39 PM PDT 24 |
May 02 03:15:48 PM PDT 24 |
572780486 ps |
| T877 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.4036498096 |
|
|
May 02 03:20:02 PM PDT 24 |
May 02 03:20:09 PM PDT 24 |
425440506 ps |
| T878 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2917727313 |
|
|
May 02 03:19:06 PM PDT 24 |
May 02 03:19:07 PM PDT 24 |
51674639 ps |
| T879 |
/workspace/coverage/default/45.sram_ctrl_executable.2815130575 |
|
|
May 02 03:23:30 PM PDT 24 |
May 02 03:32:40 PM PDT 24 |
10478100078 ps |
| T880 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4173007699 |
|
|
May 02 03:12:07 PM PDT 24 |
May 02 03:12:34 PM PDT 24 |
87713385 ps |
| T881 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1606909295 |
|
|
May 02 03:13:23 PM PDT 24 |
May 02 04:00:23 PM PDT 24 |
28404947447 ps |
| T882 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3023067416 |
|
|
May 02 03:16:40 PM PDT 24 |
May 02 03:16:47 PM PDT 24 |
137893633 ps |
| T883 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1909954376 |
|
|
May 02 03:18:33 PM PDT 24 |
May 02 03:18:45 PM PDT 24 |
2586126899 ps |
| T884 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2650112312 |
|
|
May 02 03:20:27 PM PDT 24 |
May 02 03:22:37 PM PDT 24 |
761898299 ps |
| T885 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.2954105384 |
|
|
May 02 03:17:16 PM PDT 24 |
May 02 03:26:21 PM PDT 24 |
31807547337 ps |
| T886 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1652325700 |
|
|
May 02 03:21:01 PM PDT 24 |
May 02 03:25:57 PM PDT 24 |
13345970506 ps |
| T887 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3714758531 |
|
|
May 02 03:22:40 PM PDT 24 |
May 02 03:22:50 PM PDT 24 |
76801979 ps |
| T888 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3983412533 |
|
|
May 02 03:12:49 PM PDT 24 |
May 02 03:12:55 PM PDT 24 |
469181064 ps |
| T889 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3733916329 |
|
|
May 02 03:17:21 PM PDT 24 |
May 02 03:17:23 PM PDT 24 |
31564965 ps |
| T890 |
/workspace/coverage/default/13.sram_ctrl_alert_test.55635317 |
|
|
May 02 03:15:08 PM PDT 24 |
May 02 03:15:10 PM PDT 24 |
29391584 ps |
| T891 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3508436182 |
|
|
May 02 03:15:47 PM PDT 24 |
May 02 03:31:59 PM PDT 24 |
4683506681 ps |
| T892 |
/workspace/coverage/default/37.sram_ctrl_bijection.337366028 |
|
|
May 02 03:21:18 PM PDT 24 |
May 02 03:21:43 PM PDT 24 |
1598986684 ps |
| T893 |
/workspace/coverage/default/7.sram_ctrl_smoke.2481080651 |
|
|
May 02 03:13:25 PM PDT 24 |
May 02 03:13:35 PM PDT 24 |
924584812 ps |
| T894 |
/workspace/coverage/default/23.sram_ctrl_partial_access.805020276 |
|
|
May 02 03:17:29 PM PDT 24 |
May 02 03:17:44 PM PDT 24 |
3236211573 ps |
| T895 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3935043067 |
|
|
May 02 03:23:22 PM PDT 24 |
May 02 03:23:23 PM PDT 24 |
44849654 ps |
| T896 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3598249719 |
|
|
May 02 03:22:04 PM PDT 24 |
May 02 03:24:59 PM PDT 24 |
13541802966 ps |
| T897 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3232001002 |
|
|
May 02 03:14:55 PM PDT 24 |
May 02 04:29:59 PM PDT 24 |
271331083391 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_executable.1298850527 |
|
|
May 02 03:18:25 PM PDT 24 |
May 02 03:30:19 PM PDT 24 |
21432744063 ps |
| T899 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.746635405 |
|
|
May 02 03:20:09 PM PDT 24 |
May 02 03:22:51 PM PDT 24 |
299846317 ps |
| T900 |
/workspace/coverage/default/14.sram_ctrl_regwen.2331909847 |
|
|
May 02 03:15:26 PM PDT 24 |
May 02 03:30:25 PM PDT 24 |
1361194080 ps |
| T901 |
/workspace/coverage/default/18.sram_ctrl_executable.4074258286 |
|
|
May 02 03:16:19 PM PDT 24 |
May 02 03:26:59 PM PDT 24 |
16724640385 ps |
| T902 |
/workspace/coverage/default/21.sram_ctrl_stress_all.2459014319 |
|
|
May 02 03:17:14 PM PDT 24 |
May 02 04:37:26 PM PDT 24 |
163118869514 ps |
| T903 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3616398868 |
|
|
May 02 03:15:46 PM PDT 24 |
May 02 03:16:55 PM PDT 24 |
490188054 ps |
| T904 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2786583834 |
|
|
May 02 03:17:22 PM PDT 24 |
May 02 03:23:06 PM PDT 24 |
51866901648 ps |
| T905 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1245944882 |
|
|
May 02 03:15:16 PM PDT 24 |
May 02 03:15:25 PM PDT 24 |
1536324267 ps |
| T906 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.828832102 |
|
|
May 02 03:23:29 PM PDT 24 |
May 02 03:26:13 PM PDT 24 |
1788811453 ps |
| T907 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2725604695 |
|
|
May 02 03:24:23 PM PDT 24 |
May 02 03:24:30 PM PDT 24 |
1109773775 ps |
| T908 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3456421670 |
|
|
May 02 03:23:12 PM PDT 24 |
May 02 03:23:21 PM PDT 24 |
326534774 ps |
| T909 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1022639744 |
|
|
May 02 03:23:01 PM PDT 24 |
May 02 03:29:18 PM PDT 24 |
1974874968 ps |
| T910 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2044892936 |
|
|
May 02 03:14:17 PM PDT 24 |
May 02 03:14:21 PM PDT 24 |
2189599596 ps |
| T911 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3540233437 |
|
|
May 02 03:12:29 PM PDT 24 |
May 02 03:14:02 PM PDT 24 |
133548012 ps |
| T912 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3648915903 |
|
|
May 02 03:23:34 PM PDT 24 |
May 02 03:23:36 PM PDT 24 |
44343638 ps |
| T913 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3717762209 |
|
|
May 02 03:15:28 PM PDT 24 |
May 02 03:20:12 PM PDT 24 |
12185071006 ps |
| T914 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2404907837 |
|
|
May 02 03:19:34 PM PDT 24 |
May 02 03:19:38 PM PDT 24 |
129136831 ps |
| T915 |
/workspace/coverage/default/11.sram_ctrl_regwen.2201639498 |
|
|
May 02 03:14:41 PM PDT 24 |
May 02 03:31:16 PM PDT 24 |
20719500632 ps |
| T916 |
/workspace/coverage/default/5.sram_ctrl_partial_access.841639809 |
|
|
May 02 03:12:54 PM PDT 24 |
May 02 03:14:56 PM PDT 24 |
631222869 ps |
| T917 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.379980157 |
|
|
May 02 03:21:37 PM PDT 24 |
May 02 03:21:47 PM PDT 24 |
681809363 ps |
| T918 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3161906685 |
|
|
May 02 03:22:20 PM PDT 24 |
May 02 03:22:24 PM PDT 24 |
433945662 ps |
| T919 |
/workspace/coverage/default/16.sram_ctrl_bijection.2244346589 |
|
|
May 02 03:15:40 PM PDT 24 |
May 02 03:16:02 PM PDT 24 |
926154076 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3767215675 |
|
|
May 02 03:20:34 PM PDT 24 |
May 02 03:20:36 PM PDT 24 |
267662174 ps |
| T921 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.4072834185 |
|
|
May 02 03:23:14 PM PDT 24 |
May 02 03:24:10 PM PDT 24 |
430581806 ps |
| T922 |
/workspace/coverage/default/26.sram_ctrl_smoke.3616759522 |
|
|
May 02 03:18:18 PM PDT 24 |
May 02 03:18:26 PM PDT 24 |
167095492 ps |
| T923 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1977841644 |
|
|
May 02 03:15:36 PM PDT 24 |
May 02 03:15:37 PM PDT 24 |
68381525 ps |
| T924 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2631342553 |
|
|
May 02 03:20:56 PM PDT 24 |
May 02 03:21:00 PM PDT 24 |
97475377 ps |
| T925 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1771888170 |
|
|
May 02 03:19:55 PM PDT 24 |
May 02 03:19:57 PM PDT 24 |
46639965 ps |
| T926 |
/workspace/coverage/default/0.sram_ctrl_regwen.2645048916 |
|
|
May 02 03:12:00 PM PDT 24 |
May 02 03:14:22 PM PDT 24 |
9980101706 ps |
| T927 |
/workspace/coverage/default/49.sram_ctrl_smoke.816830897 |
|
|
May 02 03:24:22 PM PDT 24 |
May 02 03:24:37 PM PDT 24 |
2897429908 ps |
| T928 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2776525842 |
|
|
May 02 03:18:03 PM PDT 24 |
May 02 03:44:21 PM PDT 24 |
39923694066 ps |
| T929 |
/workspace/coverage/default/13.sram_ctrl_bijection.3117673026 |
|
|
May 02 03:15:01 PM PDT 24 |
May 02 03:15:40 PM PDT 24 |
7279032554 ps |
| T930 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.493019306 |
|
|
May 02 03:22:49 PM PDT 24 |
May 02 03:22:58 PM PDT 24 |
366447988 ps |
| T931 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3720203494 |
|
|
May 02 03:23:40 PM PDT 24 |
May 02 03:25:44 PM PDT 24 |
446567227 ps |
| T932 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3360439101 |
|
|
May 02 03:14:57 PM PDT 24 |
May 02 03:16:27 PM PDT 24 |
4678513704 ps |
| T933 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.270665298 |
|
|
May 02 03:13:14 PM PDT 24 |
May 02 03:15:42 PM PDT 24 |
157787666 ps |
| T934 |
/workspace/coverage/default/17.sram_ctrl_regwen.3780622325 |
|
|
May 02 03:16:06 PM PDT 24 |
May 02 03:26:49 PM PDT 24 |
10172037483 ps |
| T935 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2309956420 |
|
|
May 02 03:12:50 PM PDT 24 |
May 02 03:17:19 PM PDT 24 |
75094647354 ps |
| T936 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2634546054 |
|
|
May 02 03:20:25 PM PDT 24 |
May 02 03:45:35 PM PDT 24 |
1700654841 ps |
| T937 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3520307835 |
|
|
May 02 03:17:44 PM PDT 24 |
May 02 03:17:48 PM PDT 24 |
173098338 ps |
| T938 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3862625174 |
|
|
May 02 03:23:40 PM PDT 24 |
May 02 03:23:52 PM PDT 24 |
314582146 ps |
| T939 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.235202586 |
|
|
May 02 03:53:34 PM PDT 24 |
May 02 03:53:37 PM PDT 24 |
326177024 ps |
| T91 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.819782231 |
|
|
May 02 03:53:46 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
92705735 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.151647650 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
24973884 ps |
| T59 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2518779516 |
|
|
May 02 03:53:55 PM PDT 24 |
May 02 03:53:58 PM PDT 24 |
238287382 ps |
| T60 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2582703496 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:54:01 PM PDT 24 |
16916282 ps |
| T61 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3689312932 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
46722669 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3262804822 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
625540006 ps |
| T62 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1435065022 |
|
|
May 02 03:53:41 PM PDT 24 |
May 02 03:53:45 PM PDT 24 |
1955323237 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3807942677 |
|
|
May 02 03:53:52 PM PDT 24 |
May 02 03:53:58 PM PDT 24 |
1610182888 ps |
| T64 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1299062830 |
|
|
May 02 03:53:47 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
426176775 ps |
| T65 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1995176645 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
33324079 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3174530818 |
|
|
May 02 03:53:37 PM PDT 24 |
May 02 03:53:39 PM PDT 24 |
19519845 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3209397141 |
|
|
May 02 03:53:44 PM PDT 24 |
May 02 03:53:45 PM PDT 24 |
33757463 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1421076970 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
38213220 ps |
| T68 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1777794106 |
|
|
May 02 03:53:54 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
34321610 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1574826527 |
|
|
May 02 03:53:56 PM PDT 24 |
May 02 03:53:59 PM PDT 24 |
27089537 ps |
| T93 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2446547080 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
803230472 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3345744825 |
|
|
May 02 03:53:46 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
58519684 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1378549359 |
|
|
May 02 03:53:36 PM PDT 24 |
May 02 03:53:39 PM PDT 24 |
325221910 ps |
| T94 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.487203046 |
|
|
May 02 03:54:00 PM PDT 24 |
May 02 03:54:04 PM PDT 24 |
82336996 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4040296929 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
42223787 ps |
| T944 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3516936348 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
118671293 ps |
| T945 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.819455475 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:53 PM PDT 24 |
15774091 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2066105296 |
|
|
May 02 03:53:48 PM PDT 24 |
May 02 03:53:50 PM PDT 24 |
139203255 ps |
| T73 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1484232347 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
422705022 ps |
| T947 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3471788468 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
32191035 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.680497353 |
|
|
May 02 03:53:47 PM PDT 24 |
May 02 03:53:50 PM PDT 24 |
169352642 ps |
| T103 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2537942623 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
168939320 ps |
| T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1123565490 |
|
|
May 02 03:53:42 PM PDT 24 |
May 02 03:53:44 PM PDT 24 |
47414320 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1394375305 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
80956325 ps |
| T119 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1192982619 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:55 PM PDT 24 |
2811914918 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.281869271 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
386723300 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2737864654 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
30707029 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1909363848 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:45 PM PDT 24 |
21280821 ps |
| T122 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2305776160 |
|
|
May 02 03:53:51 PM PDT 24 |
May 02 03:53:55 PM PDT 24 |
1202810206 ps |
| T74 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.72015058 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:45 PM PDT 24 |
25250070 ps |
| T952 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1466329141 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
20409793 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3467172790 |
|
|
May 02 03:53:47 PM PDT 24 |
May 02 03:53:49 PM PDT 24 |
57468443 ps |
| T954 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.357167835 |
|
|
May 02 03:53:58 PM PDT 24 |
May 02 03:54:01 PM PDT 24 |
31775943 ps |
| T120 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.947979060 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
513150713 ps |
| T75 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1174970254 |
|
|
May 02 03:53:56 PM PDT 24 |
May 02 03:53:59 PM PDT 24 |
21749332 ps |
| T955 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4182518272 |
|
|
May 02 03:53:40 PM PDT 24 |
May 02 03:53:43 PM PDT 24 |
117328273 ps |
| T956 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3951934286 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:54:00 PM PDT 24 |
108122351 ps |
| T76 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3068350192 |
|
|
May 02 03:53:44 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
1776620612 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4252239847 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
41118262 ps |
| T77 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2983782392 |
|
|
May 02 03:53:54 PM PDT 24 |
May 02 03:54:00 PM PDT 24 |
708067936 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4113108582 |
|
|
May 02 03:53:33 PM PDT 24 |
May 02 03:53:35 PM PDT 24 |
143323924 ps |
| T959 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.568647670 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:49 PM PDT 24 |
310325784 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2768024196 |
|
|
May 02 03:53:51 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
72193984 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2829076909 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:54:00 PM PDT 24 |
1659529250 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.219114749 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
39126116 ps |
| T123 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3734813577 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:55 PM PDT 24 |
313685385 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2950940429 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
37021965 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2261733572 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
82264993 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3949712170 |
|
|
May 02 03:53:56 PM PDT 24 |
May 02 03:54:00 PM PDT 24 |
206943035 ps |
| T85 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2404291344 |
|
|
May 02 03:53:56 PM PDT 24 |
May 02 03:54:00 PM PDT 24 |
208571862 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1622248470 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:50 PM PDT 24 |
112426531 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2989749431 |
|
|
May 02 03:53:52 PM PDT 24 |
May 02 03:53:56 PM PDT 24 |
45247834 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.384386553 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
168911013 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2926641101 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
16108027 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1614727970 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:47 PM PDT 24 |
26954193 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3357560145 |
|
|
May 02 03:53:42 PM PDT 24 |
May 02 03:53:44 PM PDT 24 |
22211796 ps |
| T969 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3873030515 |
|
|
May 02 03:54:04 PM PDT 24 |
May 02 03:54:09 PM PDT 24 |
134382344 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2085820584 |
|
|
May 02 03:53:55 PM PDT 24 |
May 02 03:53:58 PM PDT 24 |
14566835 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2551268537 |
|
|
May 02 03:53:47 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
437709003 ps |
| T87 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2116299305 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:59 PM PDT 24 |
532329174 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.985458874 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
179352280 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3285199858 |
|
|
May 02 03:53:34 PM PDT 24 |
May 02 03:53:35 PM PDT 24 |
43214069 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1429284014 |
|
|
May 02 03:54:05 PM PDT 24 |
May 02 03:54:11 PM PDT 24 |
496961607 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3314814565 |
|
|
May 02 03:54:01 PM PDT 24 |
May 02 03:54:08 PM PDT 24 |
194129176 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3349894811 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
15994630 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3168927552 |
|
|
May 02 03:53:46 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
17026989 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2083700782 |
|
|
May 02 03:54:07 PM PDT 24 |
May 02 03:54:11 PM PDT 24 |
37101743 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1203122532 |
|
|
May 02 03:53:48 PM PDT 24 |
May 02 03:53:53 PM PDT 24 |
125066020 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3420622820 |
|
|
May 02 03:53:52 PM PDT 24 |
May 02 03:53:56 PM PDT 24 |
19778223 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4031577192 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
99218904 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2027816598 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:49 PM PDT 24 |
129540287 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.754763960 |
|
|
May 02 03:53:41 PM PDT 24 |
May 02 03:53:44 PM PDT 24 |
33811956 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.408798130 |
|
|
May 02 03:54:00 PM PDT 24 |
May 02 03:54:04 PM PDT 24 |
27585196 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.842294114 |
|
|
May 02 03:53:56 PM PDT 24 |
May 02 03:54:01 PM PDT 24 |
416830538 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2585886286 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:54 PM PDT 24 |
49533008 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2083110085 |
|
|
May 02 03:53:53 PM PDT 24 |
May 02 03:53:58 PM PDT 24 |
79364695 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3930005832 |
|
|
May 02 03:53:54 PM PDT 24 |
May 02 03:53:57 PM PDT 24 |
40648328 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1468575210 |
|
|
May 02 03:53:34 PM PDT 24 |
May 02 03:53:38 PM PDT 24 |
450274813 ps |
| T127 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1296792065 |
|
|
May 02 03:53:54 PM PDT 24 |
May 02 03:53:59 PM PDT 24 |
973879380 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2188713179 |
|
|
May 02 03:54:07 PM PDT 24 |
May 02 03:54:12 PM PDT 24 |
602524754 ps |
| T988 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3793070421 |
|
|
May 02 03:53:44 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
466352868 ps |
| T989 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3793056498 |
|
|
May 02 03:53:56 PM PDT 24 |
May 02 03:54:03 PM PDT 24 |
70247684 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1400205253 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:51 PM PDT 24 |
45001091 ps |
| T128 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2385693188 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
552835198 ps |
| T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3318220957 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:55 PM PDT 24 |
141607615 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4204896677 |
|
|
May 02 03:53:48 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
224299644 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3710203641 |
|
|
May 02 03:53:54 PM PDT 24 |
May 02 03:53:58 PM PDT 24 |
26344238 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3316436080 |
|
|
May 02 03:53:51 PM PDT 24 |
May 02 03:53:56 PM PDT 24 |
309931345 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.214359886 |
|
|
May 02 03:53:55 PM PDT 24 |
May 02 03:53:58 PM PDT 24 |
15823214 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2255943077 |
|
|
May 02 03:53:35 PM PDT 24 |
May 02 03:53:37 PM PDT 24 |
23845433 ps |
| T996 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.396107442 |
|
|
May 02 03:53:49 PM PDT 24 |
May 02 03:53:52 PM PDT 24 |
36047508 ps |
| T129 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1278098020 |
|
|
May 02 03:53:51 PM PDT 24 |
May 02 03:53:56 PM PDT 24 |
292988358 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1063037910 |
|
|
May 02 03:53:58 PM PDT 24 |
May 02 03:54:02 PM PDT 24 |
159738396 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1362928617 |
|
|
May 02 03:53:55 PM PDT 24 |
May 02 03:54:00 PM PDT 24 |
123813109 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.175192795 |
|
|
May 02 03:53:45 PM PDT 24 |
May 02 03:53:50 PM PDT 24 |
1417185141 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2797898157 |
|
|
May 02 03:53:44 PM PDT 24 |
May 02 03:53:48 PM PDT 24 |
259103158 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1059966856 |
|
|
May 02 03:53:43 PM PDT 24 |
May 02 03:53:45 PM PDT 24 |
787662275 ps |
| T1001 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1598154203 |
|
|
May 02 03:53:51 PM PDT 24 |
May 02 03:53:56 PM PDT 24 |
90738009 ps |
| T130 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1895294059 |
|
|
May 02 03:53:50 PM PDT 24 |
May 02 03:53:53 PM PDT 24 |
266859136 ps |