Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	136482378	1			T1	13342		T2	67268		T3	18828
instr_valid_dis	109925681	1			T1	13342		T2	67268		T3	18828
instr_en	18162690	1			T4	45356		T18	4544		T59	113206

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	7442419	1			T4	500		T17	144614		T18	18848
sram_ifetch_valid_disable	109202578	1			T1	13342		T2	67268		T3	18828
sram_ifetch_enable	19837381	1			T4	65416		T17	264074		T18	15326

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	136482378	1			T1	13342		T2	67268		T3	18828
hw_debug_en_valid_off	110061601	1			T1	13342		T2	67268		T3	18828
hw_debug_en_on	17963944	1			T4	20000		T17	250500		T18	36042

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109202578	1			T1	13342		T2	67268		T3	18828
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99222036	1			T1	13342		T2	67268		T3	18828
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	6757117	1			T59	42786		T6	94928		T135	9040
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3069314	1			T4	500		T17	30344		T59	35532
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1242328	1			T4	500		T29	25030		T142	14238
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1341162	1			T59	35532		T63	59476		T143	13670
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2977046	1			T17	114270		T18	8638		T61	75644
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1225448	1			T18	4094		T29	20000		T144	9508
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1117380	1			T18	4544		T63	16200		T137	74588
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6434336	1			T17	72404		T18	26246		T59	35760
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3293860	1			T18	26246		T6	20166		T7	26998
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2210706	1			T59	35760		T6	20000		T29	9652

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8268715	1			T4	45356		T59	34888		T6	99678
lc_exec_en	8552562	1			T4	20000		T17	63826		T18	1158
valid_exec_dis	106749776	1			T1	13342		T2	67268		T3	18828
invalid_exec_dis	27279800	1			T4	65916		T17	408688		T18	34174