Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42242817	1			T1	6671		T2	30599		T3	7666
triple_byte_access	2445346	1			T2	637		T3	364		T4	286
halfword_access	3667813	1			T2	868		T3	507		T4	444
byte_access	4903022	1			T2	1219		T3	699		T4	527
zero_access	1232509	1			T2	311		T3	178		T4	141

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27180707

1

T1

3255

T2

16808

T3

4667

auto[1]

27310800

1

T1

3416

T2

16826

T3

4747

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21061854	1			T1	3255		T2	15291		T3	3790
auto[0]	triple_byte_access	1218224	1			T2	303		T3	184		T4	130
auto[0]	halfword_access	1829353	1			T2	441		T3	256		T4	207
auto[0]	byte_access	2450656	1			T2	604		T3	347		T4	257
auto[0]	zero_access	620620	1			T2	169		T3	90		T4	70
auto[1]	word_access	21180963	1			T1	3416		T2	15308		T3	3876
auto[1]	triple_byte_access	1227122	1			T2	334		T3	180		T4	156
auto[1]	halfword_access	1838460	1			T2	427		T3	251		T4	237
auto[1]	byte_access	2452366	1			T2	615		T3	352		T4	270
auto[1]	zero_access	611889	1			T2	142		T3	88		T4	71