Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	140035464	1			T2	403568		T3	81920		T4	375370
instr_valid_dis	109882301	1			T3	81920		T4	375370		T5	6830
instr_en	23471914	1			T2	403568		T11	479970		T19	13956

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10421278	1			T2	176950		T11	172232		T19	81148
sram_ifetch_valid_disable	109850309	1			T2	97872		T3	81920		T4	375370
sram_ifetch_enable	19763877	1			T2	128746		T11	217272		T19	8030

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	140035464	1			T2	403568		T3	81920		T4	375370
hw_debug_en_valid_off	110388980	1			T2	224980		T3	81920		T4	375370
hw_debug_en_on	20694206	1			T2	102426		T11	215062		T19	126366

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109850309	1			T2	97872		T3	81920		T4	375370
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97713783	1			T3	81920		T4	375370		T5	6830
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9581961	1			T2	97872		T11	90466		T19	13956
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4045594	1			T2	137230		T11	114004		T6	8676
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1637062	1			T6	8676		T38	82678		T124	35586
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1863528	1			T2	137230		T11	114004		T120	61770
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4488768	1			T2	39720		T11	38228		T19	81148
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1474678	1			T38	37004		T123	9050		T132	18286
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2197006	1			T2	39720		T11	38228		T6	288290
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7748670	1			T2	32672		T11	22508		T19	45218
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2833842	1			T19	45218		T38	6394		T120	52610
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3960410	1			T2	32672		T11	22508		T6	92530

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9163093	1			T2	128746		T11	217272		T6	109956
lc_exec_en	8456768	1			T2	30034		T11	154326		T21	11072
valid_exec_dis	106735329	1			T2	29052		T3	81920		T4	375370
invalid_exec_dis	30185155	1			T2	305696		T11	389504		T19	89178