Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total tests in report: 1024
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.35 85.35 97.66 97.66 78.57 78.57 93.56 93.56 100.00 100.00 91.35 91.35 94.75 94.75 41.56 41.56 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2940408151
93.89 8.53 99.32 1.66 87.66 9.09 98.21 4.65 100.00 0.00 95.39 4.03 96.10 1.35 80.52 38.96 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.499946848
95.56 1.67 99.32 0.00 90.39 2.73 98.21 0.00 100.00 0.00 97.12 1.73 96.10 0.00 87.76 7.24 /workspace/coverage/default/37.sram_ctrl_stress_all.2614572937
96.53 0.97 99.71 0.39 92.60 2.21 99.14 0.93 100.00 0.00 98.85 1.73 96.70 0.60 88.68 0.93 /workspace/coverage/default/1.sram_ctrl_sec_cm.3956700961
97.30 0.77 99.71 0.00 92.99 0.39 99.14 0.00 100.00 0.00 98.85 0.00 96.70 0.00 93.69 5.01 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2353657635
97.64 0.35 99.71 0.00 93.25 0.26 99.14 0.00 100.00 0.00 98.85 0.00 97.75 1.05 94.81 1.11 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1408240669
97.91 0.27 99.71 0.00 93.51 0.26 99.21 0.07 100.00 0.00 98.85 0.00 98.95 1.20 95.18 0.37 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1031333326
98.08 0.17 99.71 0.00 93.77 0.26 99.21 0.00 100.00 0.00 98.85 0.00 98.95 0.00 96.10 0.93 /workspace/coverage/default/5.sram_ctrl_stress_all.210333088
98.22 0.13 99.71 0.00 93.77 0.00 99.21 0.00 100.00 0.00 98.85 0.00 98.95 0.00 97.03 0.93 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3007573911
98.33 0.12 99.81 0.10 93.77 0.00 99.93 0.72 100.00 0.00 98.85 0.00 98.95 0.00 97.03 0.00 /workspace/coverage/default/10.sram_ctrl_ram_cfg.1642055523
98.42 0.09 99.81 0.00 93.77 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.40 0.45 97.22 0.19 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3621523720
98.50 0.08 99.81 0.00 93.77 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.40 0.00 97.77 0.56 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.645015439
98.57 0.07 99.81 0.00 94.16 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.40 0.00 97.77 0.00 /workspace/coverage/default/14.sram_ctrl_alert_test.2087170054
98.62 0.05 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.15 97.96 0.19 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2844287254
98.64 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.14 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1191539636
98.67 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2932523230
98.70 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3573639505
98.72 0.02 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3440648517

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2345599974
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2318794027
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3909490522
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4277780624
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3149457180
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3829382425
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1254577643
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2736252304
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.46700093
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2877663205
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3063410544
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3529144600
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1665761442
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1336152275
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4236970711
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1461345866
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3547150035
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3171730348
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3071911639
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2900772844
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3122408404
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3616205325
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3599169937
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2989905380
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3645607060
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3046039328
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1754132664
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3645580419
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3814687056
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.989938941
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2622536464
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2629431792
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1372968447
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1329672687
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4074895734
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1078843850
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1613457158
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1092461714
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2736651470
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.428720603
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2634658568
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2590796561
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2398756556
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2292785844
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1626835103
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.304701633
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1587776840
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1404763767
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3848638518
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4106087114
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2495150551
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3962528631
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4153410861
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.767766588
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2633393628
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4159289863
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2186947004
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.308921798
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.856154150
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2474483269
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.131746727
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3545915393
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1546466230
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1259137994
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4160038720
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1917018000
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3720123152
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3133521595
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2994498692
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1398966552
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3239440114
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3653451121
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3553154044
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.435124382
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3813514905
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.568169675
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3523634473
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1391362522
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3274718220
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1328162610
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3440381451
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1609952884
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3486432669
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3223099742
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1666284647
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.224642152
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3885344251
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3486150082
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1162291658
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.639012073
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3317608059
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1453327059
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3419307214
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2695795793
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3370793940
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1863275632
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2783773953
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2371920486
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2517185576
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1234718773
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.862287650
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3628505888
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4268437747
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2691304086
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.552700037
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2755890427
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.901699609
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1359756465
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4219193571
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2905084673
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1659696261
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.878209321
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.386506898
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1424190821
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1379321791
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3589970198
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2327004409
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.397122476
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1684125332
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.24524995
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.694116979
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.581513997
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3826872517
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1043856093
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2337288853
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.708359927
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2480858453
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1721299730
/workspace/coverage/default/0.sram_ctrl_alert_test.64239569
/workspace/coverage/default/0.sram_ctrl_bijection.1882763538
/workspace/coverage/default/0.sram_ctrl_executable.2433628165
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2836536354
/workspace/coverage/default/0.sram_ctrl_max_throughput.1927221454
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3432539024
/workspace/coverage/default/0.sram_ctrl_mem_walk.4221452938
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3757325018
/workspace/coverage/default/0.sram_ctrl_partial_access.2067425056
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1156021545
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3145107393
/workspace/coverage/default/0.sram_ctrl_regwen.1110093486
/workspace/coverage/default/0.sram_ctrl_sec_cm.436063408
/workspace/coverage/default/0.sram_ctrl_smoke.1493650784
/workspace/coverage/default/0.sram_ctrl_stress_all.3582543013
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2010382910
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.517387604
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.951589840
/workspace/coverage/default/1.sram_ctrl_alert_test.1228576496
/workspace/coverage/default/1.sram_ctrl_bijection.345869405
/workspace/coverage/default/1.sram_ctrl_executable.2280680617
/workspace/coverage/default/1.sram_ctrl_lc_escalation.93363689
/workspace/coverage/default/1.sram_ctrl_max_throughput.2867128449
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2297202323
/workspace/coverage/default/1.sram_ctrl_mem_walk.1494002311
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3131361715
/workspace/coverage/default/1.sram_ctrl_partial_access.1155352354
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.511716703
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3283626798
/workspace/coverage/default/1.sram_ctrl_regwen.850452188
/workspace/coverage/default/1.sram_ctrl_smoke.2572162311
/workspace/coverage/default/1.sram_ctrl_stress_all.3593482334
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1511034205
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1348089980
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1075542926
/workspace/coverage/default/10.sram_ctrl_alert_test.2630057908
/workspace/coverage/default/10.sram_ctrl_bijection.1471226910
/workspace/coverage/default/10.sram_ctrl_executable.4176464397
/workspace/coverage/default/10.sram_ctrl_lc_escalation.683843971
/workspace/coverage/default/10.sram_ctrl_max_throughput.1792620066
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.756790337
/workspace/coverage/default/10.sram_ctrl_mem_walk.2414778208
/workspace/coverage/default/10.sram_ctrl_multiple_keys.736985170
/workspace/coverage/default/10.sram_ctrl_partial_access.2524727919
/workspace/coverage/default/10.sram_ctrl_regwen.1270401553
/workspace/coverage/default/10.sram_ctrl_smoke.4000521173
/workspace/coverage/default/10.sram_ctrl_stress_all.2434213238
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2110221939
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1604138560
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4058494123
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.773191205
/workspace/coverage/default/11.sram_ctrl_alert_test.3277220149
/workspace/coverage/default/11.sram_ctrl_bijection.3684545406
/workspace/coverage/default/11.sram_ctrl_executable.3616936181
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2622372689
/workspace/coverage/default/11.sram_ctrl_max_throughput.3398795888
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3548016303
/workspace/coverage/default/11.sram_ctrl_mem_walk.455736629
/workspace/coverage/default/11.sram_ctrl_multiple_keys.224812162
/workspace/coverage/default/11.sram_ctrl_partial_access.1019035202
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2365806761
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2758299146
/workspace/coverage/default/11.sram_ctrl_regwen.3279185983
/workspace/coverage/default/11.sram_ctrl_smoke.2299302908
/workspace/coverage/default/11.sram_ctrl_stress_all.677563541
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2128641286
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3207026324
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1645967564
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3900187157
/workspace/coverage/default/12.sram_ctrl_alert_test.4249462192
/workspace/coverage/default/12.sram_ctrl_bijection.800733358
/workspace/coverage/default/12.sram_ctrl_executable.4093340490
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2618881282
/workspace/coverage/default/12.sram_ctrl_max_throughput.2855943351
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.692239620
/workspace/coverage/default/12.sram_ctrl_mem_walk.1897034313
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2083602454
/workspace/coverage/default/12.sram_ctrl_partial_access.797317013
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3960463945
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2840096420
/workspace/coverage/default/12.sram_ctrl_regwen.394324972
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/workspace/coverage/default/43.sram_ctrl_ram_cfg.2535935840
/workspace/coverage/default/43.sram_ctrl_regwen.721417059
/workspace/coverage/default/43.sram_ctrl_smoke.641633339
/workspace/coverage/default/43.sram_ctrl_stress_all.3215145278
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.522204971
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1070429240
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2477164766
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.37455389
/workspace/coverage/default/44.sram_ctrl_alert_test.1621717369
/workspace/coverage/default/44.sram_ctrl_bijection.3870125341
/workspace/coverage/default/44.sram_ctrl_executable.3077064813
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1037641179
/workspace/coverage/default/44.sram_ctrl_max_throughput.2432101712
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.540626951
/workspace/coverage/default/44.sram_ctrl_mem_walk.1533608779
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1871177980
/workspace/coverage/default/44.sram_ctrl_partial_access.1420086957
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.925789620
/workspace/coverage/default/44.sram_ctrl_ram_cfg.560291449
/workspace/coverage/default/44.sram_ctrl_regwen.3566765167
/workspace/coverage/default/44.sram_ctrl_smoke.2528001641
/workspace/coverage/default/44.sram_ctrl_stress_all.3691205590
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3625963416
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.21089216
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.384837729
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1928482311
/workspace/coverage/default/45.sram_ctrl_alert_test.2159893665
/workspace/coverage/default/45.sram_ctrl_bijection.2391358739
/workspace/coverage/default/45.sram_ctrl_executable.3824258902
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2721497558
/workspace/coverage/default/45.sram_ctrl_max_throughput.4154581110
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.64043772
/workspace/coverage/default/45.sram_ctrl_mem_walk.3397418940
/workspace/coverage/default/45.sram_ctrl_multiple_keys.326363290
/workspace/coverage/default/45.sram_ctrl_partial_access.3228409476
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2107631986
/workspace/coverage/default/45.sram_ctrl_ram_cfg.810672226
/workspace/coverage/default/45.sram_ctrl_regwen.798045067
/workspace/coverage/default/45.sram_ctrl_smoke.1247253360
/workspace/coverage/default/45.sram_ctrl_stress_all.2402782745
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3587181048
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4245412154
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3527949758
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1963874957
/workspace/coverage/default/46.sram_ctrl_alert_test.2379260653
/workspace/coverage/default/46.sram_ctrl_bijection.2686678505
/workspace/coverage/default/46.sram_ctrl_executable.2707637157
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1487127206
/workspace/coverage/default/46.sram_ctrl_max_throughput.3740448667
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.128207425
/workspace/coverage/default/46.sram_ctrl_mem_walk.1715888862
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2464710314
/workspace/coverage/default/46.sram_ctrl_partial_access.3683260240
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3019893810
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2504634704
/workspace/coverage/default/46.sram_ctrl_regwen.371711695
/workspace/coverage/default/46.sram_ctrl_smoke.3717070530
/workspace/coverage/default/46.sram_ctrl_stress_all.528069540
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3905533497
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1685669883
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2285015820
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.786329003
/workspace/coverage/default/47.sram_ctrl_alert_test.4163821592
/workspace/coverage/default/47.sram_ctrl_bijection.3222000618
/workspace/coverage/default/47.sram_ctrl_executable.4061106110
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1075641540
/workspace/coverage/default/47.sram_ctrl_max_throughput.2572341835
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.860225497
/workspace/coverage/default/47.sram_ctrl_mem_walk.2478539529
/workspace/coverage/default/47.sram_ctrl_multiple_keys.412263238
/workspace/coverage/default/47.sram_ctrl_partial_access.865618245
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.907758997
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1400013234
/workspace/coverage/default/47.sram_ctrl_regwen.4262162136
/workspace/coverage/default/47.sram_ctrl_smoke.965549177
/workspace/coverage/default/47.sram_ctrl_stress_all.1322034961
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3260613320
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.829416627
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2208632978
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3451739384
/workspace/coverage/default/48.sram_ctrl_alert_test.4206616761
/workspace/coverage/default/48.sram_ctrl_bijection.276390620
/workspace/coverage/default/48.sram_ctrl_executable.1265214325
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1115097198
/workspace/coverage/default/48.sram_ctrl_max_throughput.3954897333
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2554795657
/workspace/coverage/default/48.sram_ctrl_mem_walk.482545201
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2182470182
/workspace/coverage/default/48.sram_ctrl_partial_access.3534298012
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3445820394
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2631525802
/workspace/coverage/default/48.sram_ctrl_regwen.3278522955
/workspace/coverage/default/48.sram_ctrl_smoke.2137428288
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2058564856
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1372727519
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.921451945
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.315753631
/workspace/coverage/default/49.sram_ctrl_alert_test.2762364364
/workspace/coverage/default/49.sram_ctrl_bijection.381478648
/workspace/coverage/default/49.sram_ctrl_executable.4056334896
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2526953222
/workspace/coverage/default/49.sram_ctrl_max_throughput.4186734822
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3145157921
/workspace/coverage/default/49.sram_ctrl_mem_walk.3965455389
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3792401282
/workspace/coverage/default/49.sram_ctrl_partial_access.2712465997
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.48941343
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3700769028
/workspace/coverage/default/49.sram_ctrl_regwen.457364690
/workspace/coverage/default/49.sram_ctrl_smoke.1855885513
/workspace/coverage/default/49.sram_ctrl_stress_all.676044467
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.748374559
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3913095675
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2897300569
/workspace/coverage/default/5.sram_ctrl_alert_test.2922141944
/workspace/coverage/default/5.sram_ctrl_bijection.2687244496
/workspace/coverage/default/5.sram_ctrl_executable.4037844339
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2559510969
/workspace/coverage/default/5.sram_ctrl_max_throughput.1667213159
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1312669870
/workspace/coverage/default/5.sram_ctrl_mem_walk.860217718
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1612877667
/workspace/coverage/default/5.sram_ctrl_partial_access.2369471379
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3741853725
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3432386777
/workspace/coverage/default/5.sram_ctrl_regwen.3562200718
/workspace/coverage/default/5.sram_ctrl_smoke.3445151554
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.708377942
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.564659780
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.494099788
/workspace/coverage/default/6.sram_ctrl_alert_test.3031844869
/workspace/coverage/default/6.sram_ctrl_bijection.1174593933
/workspace/coverage/default/6.sram_ctrl_executable.1745281883
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3627104156
/workspace/coverage/default/6.sram_ctrl_max_throughput.297345920
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1220349690
/workspace/coverage/default/6.sram_ctrl_mem_walk.1742267722
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2156894356
/workspace/coverage/default/6.sram_ctrl_partial_access.2728334130
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3404885111
/workspace/coverage/default/6.sram_ctrl_ram_cfg.278359303
/workspace/coverage/default/6.sram_ctrl_regwen.2333786945
/workspace/coverage/default/6.sram_ctrl_smoke.1844692044
/workspace/coverage/default/6.sram_ctrl_stress_all.1442436336
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2911044930
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1499724779
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.219042964
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1206114488
/workspace/coverage/default/7.sram_ctrl_alert_test.3024402514
/workspace/coverage/default/7.sram_ctrl_bijection.2621635077
/workspace/coverage/default/7.sram_ctrl_executable.1102205748
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2454462779
/workspace/coverage/default/7.sram_ctrl_max_throughput.1218069182
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3879027410
/workspace/coverage/default/7.sram_ctrl_mem_walk.1906875800
/workspace/coverage/default/7.sram_ctrl_multiple_keys.958312819
/workspace/coverage/default/7.sram_ctrl_partial_access.3952302908
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.553627937
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1622287321
/workspace/coverage/default/7.sram_ctrl_regwen.1033294330
/workspace/coverage/default/7.sram_ctrl_smoke.2180626300
/workspace/coverage/default/7.sram_ctrl_stress_all.756734153
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2287725120
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.807384984
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1880978969
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2242769724
/workspace/coverage/default/8.sram_ctrl_alert_test.773721181
/workspace/coverage/default/8.sram_ctrl_bijection.4088832847
/workspace/coverage/default/8.sram_ctrl_executable.2095179722
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2713482482
/workspace/coverage/default/8.sram_ctrl_max_throughput.212765665
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.892927292
/workspace/coverage/default/8.sram_ctrl_mem_walk.2725489977
/workspace/coverage/default/8.sram_ctrl_multiple_keys.990937307
/workspace/coverage/default/8.sram_ctrl_partial_access.1338678443
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4153860896
/workspace/coverage/default/8.sram_ctrl_ram_cfg.832708087
/workspace/coverage/default/8.sram_ctrl_regwen.3675970288
/workspace/coverage/default/8.sram_ctrl_smoke.1233251281
/workspace/coverage/default/8.sram_ctrl_stress_all.1337125607
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1666984801
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3039380325
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.986376520
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3051686312
/workspace/coverage/default/9.sram_ctrl_alert_test.365004605
/workspace/coverage/default/9.sram_ctrl_bijection.2029105291
/workspace/coverage/default/9.sram_ctrl_executable.268346577
/workspace/coverage/default/9.sram_ctrl_lc_escalation.786024305
/workspace/coverage/default/9.sram_ctrl_max_throughput.2894557842
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1206483262
/workspace/coverage/default/9.sram_ctrl_mem_walk.854575281
/workspace/coverage/default/9.sram_ctrl_multiple_keys.471440861
/workspace/coverage/default/9.sram_ctrl_partial_access.416964147
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1714084206
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1380772134
/workspace/coverage/default/9.sram_ctrl_regwen.456576382
/workspace/coverage/default/9.sram_ctrl_smoke.1404089214
/workspace/coverage/default/9.sram_ctrl_stress_all.677919556
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2261247672
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4258514132
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.205192246



Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/28.sram_ctrl_ram_cfg.2840439537 May 12 12:59:02 PM PDT 24 May 12 12:59:04 PM PDT 24 69373378 ps
T2 /workspace/coverage/default/32.sram_ctrl_regwen.3965144696 May 12 12:59:23 PM PDT 24 May 12 01:12:18 PM PDT 24 56661412541 ps
T3 /workspace/coverage/default/7.sram_ctrl_bijection.2621635077 May 12 12:58:38 PM PDT 24 May 12 12:59:34 PM PDT 24 3510574660 ps
T4 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.249383542 May 12 12:58:54 PM PDT 24 May 12 01:02:26 PM PDT 24 2339729527 ps
T5 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2940408151 May 12 12:59:25 PM PDT 24 May 12 12:59:31 PM PDT 24 573977877 ps
T9 /workspace/coverage/default/29.sram_ctrl_partial_access.709938303 May 12 12:59:11 PM PDT 24 May 12 12:59:13 PM PDT 24 132535651 ps
T10 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1408240669 May 12 12:58:34 PM PDT 24 May 12 01:16:47 PM PDT 24 12876693875 ps
T11 /workspace/coverage/default/29.sram_ctrl_regwen.655987937 May 12 12:59:04 PM PDT 24 May 12 01:24:09 PM PDT 24 16150922331 ps
T12 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.873407974 May 12 12:59:06 PM PDT 24 May 12 01:00:18 PM PDT 24 8092113566 ps
T13 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2995936420 May 12 12:58:52 PM PDT 24 May 12 12:58:53 PM PDT 24 33561559 ps
T18 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2297202323 May 12 12:58:09 PM PDT 24 May 12 12:58:17 PM PDT 24 236928782 ps
T24 /workspace/coverage/default/14.sram_ctrl_alert_test.2087170054 May 12 12:58:37 PM PDT 24 May 12 12:58:38 PM PDT 24 16651174 ps
T19 /workspace/coverage/default/33.sram_ctrl_executable.252754369 May 12 12:59:28 PM PDT 24 May 12 01:06:34 PM PDT 24 25415210315 ps
T20 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3114190763 May 12 12:59:33 PM PDT 24 May 12 01:14:25 PM PDT 24 6704611679 ps
T49 /workspace/coverage/default/6.sram_ctrl_smoke.1844692044 May 12 12:58:46 PM PDT 24 May 12 12:59:14 PM PDT 24 324644089 ps
T50 /workspace/coverage/default/21.sram_ctrl_max_throughput.995511133 May 12 12:58:59 PM PDT 24 May 12 12:59:12 PM PDT 24 237775807 ps
T15 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.412519016 May 12 12:59:52 PM PDT 24 May 12 01:04:34 PM PDT 24 5596812394 ps
T51 /workspace/coverage/default/1.sram_ctrl_partial_access.1155352354 May 12 12:58:15 PM PDT 24 May 12 12:58:24 PM PDT 24 862352532 ps
T21 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.499946848 May 12 12:58:23 PM PDT 24 May 12 01:03:04 PM PDT 24 1275217851 ps
T135 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3013711483 May 12 12:58:53 PM PDT 24 May 12 01:17:57 PM PDT 24 2754950574 ps
T17 /workspace/coverage/default/43.sram_ctrl_bijection.181148045 May 12 12:59:59 PM PDT 24 May 12 01:01:09 PM PDT 24 7824191248 ps
T27 /workspace/coverage/default/12.sram_ctrl_regwen.394324972 May 12 12:58:29 PM PDT 24 May 12 01:02:01 PM PDT 24 5860590200 ps
T6 /workspace/coverage/default/8.sram_ctrl_stress_all.1337125607 May 12 12:58:35 PM PDT 24 May 12 01:32:27 PM PDT 24 95344021487 ps
T64 /workspace/coverage/default/29.sram_ctrl_smoke.3903048230 May 12 12:59:02 PM PDT 24 May 12 01:00:11 PM PDT 24 397140787 ps
T149 /workspace/coverage/default/12.sram_ctrl_multiple_keys.2083602454 May 12 12:58:35 PM PDT 24 May 12 01:16:18 PM PDT 24 101386947540 ps
T14 /workspace/coverage/default/42.sram_ctrl_partial_access.3210287722 May 12 12:59:56 PM PDT 24 May 12 12:59:59 PM PDT 24 467020136 ps
T8 /workspace/coverage/default/1.sram_ctrl_sec_cm.3956700961 May 12 12:58:16 PM PDT 24 May 12 12:58:20 PM PDT 24 1181599575 ps
T33 /workspace/coverage/default/33.sram_ctrl_max_throughput.1611786463 May 12 12:59:31 PM PDT 24 May 12 12:59:34 PM PDT 24 185572126 ps
T34 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2844287254 May 12 12:58:12 PM PDT 24 May 12 01:04:01 PM PDT 24 3628683255 ps
T7 /workspace/coverage/default/9.sram_ctrl_lc_escalation.786024305 May 12 12:58:37 PM PDT 24 May 12 12:58:47 PM PDT 24 838479380 ps
T35 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.656318239 May 12 12:58:58 PM PDT 24 May 12 01:06:15 PM PDT 24 69569553972 ps
T36 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.131961882 May 12 12:59:06 PM PDT 24 May 12 01:04:29 PM PDT 24 7865153074 ps
T16 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2610612236 May 12 12:59:55 PM PDT 24 May 12 01:10:35 PM PDT 24 115678427569 ps
T37 /workspace/coverage/default/43.sram_ctrl_mem_walk.1324249853 May 12 01:00:03 PM PDT 24 May 12 01:00:12 PM PDT 24 285880541 ps
T38 /workspace/coverage/default/37.sram_ctrl_stress_all.2614572937 May 12 12:59:40 PM PDT 24 May 12 02:29:36 PM PDT 24 70014836669 ps
T39 /workspace/coverage/default/42.sram_ctrl_mem_walk.2556227585 May 12 01:00:01 PM PDT 24 May 12 01:00:10 PM PDT 24 912878417 ps
T87 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.4139946065 May 12 12:58:51 PM PDT 24 May 12 01:03:05 PM PDT 24 11351981007 ps
T134 /workspace/coverage/default/0.sram_ctrl_bijection.1882763538 May 12 12:58:08 PM PDT 24 May 12 12:59:07 PM PDT 24 3965652531 ps
T129 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1070751136 May 12 12:59:50 PM PDT 24 May 12 01:13:13 PM PDT 24 50712567768 ps
T143 /workspace/coverage/default/35.sram_ctrl_bijection.3862039481 May 12 12:59:34 PM PDT 24 May 12 12:59:49 PM PDT 24 1011664231 ps
T150 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.339033500 May 12 12:59:11 PM PDT 24 May 12 01:01:41 PM PDT 24 596116721 ps
T136 /workspace/coverage/default/41.sram_ctrl_multiple_keys.3674903311 May 12 12:59:50 PM PDT 24 May 12 01:21:34 PM PDT 24 14156950024 ps
T25 /workspace/coverage/default/20.sram_ctrl_alert_test.694529805 May 12 12:59:04 PM PDT 24 May 12 12:59:07 PM PDT 24 12531221 ps
T151 /workspace/coverage/default/26.sram_ctrl_smoke.3465649570 May 12 12:59:05 PM PDT 24 May 12 01:00:24 PM PDT 24 153732103 ps
T29 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.4124127903 May 12 12:59:52 PM PDT 24 May 12 01:11:55 PM PDT 24 5210035297 ps
T152 /workspace/coverage/default/12.sram_ctrl_max_throughput.2855943351 May 12 12:58:36 PM PDT 24 May 12 12:59:16 PM PDT 24 1865178115 ps
T120 /workspace/coverage/default/9.sram_ctrl_executable.268346577 May 12 12:58:35 PM PDT 24 May 12 01:16:08 PM PDT 24 61323986791 ps
T153 /workspace/coverage/default/25.sram_ctrl_max_throughput.2594665284 May 12 12:59:02 PM PDT 24 May 12 12:59:42 PM PDT 24 418797092 ps
T154 /workspace/coverage/default/19.sram_ctrl_smoke.3907278690 May 12 12:58:54 PM PDT 24 May 12 12:59:15 PM PDT 24 572452667 ps
T88 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.807384984 May 12 12:58:10 PM PDT 24 May 12 01:00:09 PM PDT 24 1228845108 ps
T155 /workspace/coverage/default/18.sram_ctrl_partial_access.2953813802 May 12 12:58:55 PM PDT 24 May 12 01:00:33 PM PDT 24 8402492929 ps
T52 /workspace/coverage/default/13.sram_ctrl_lc_escalation.71177871 May 12 12:58:50 PM PDT 24 May 12 12:58:56 PM PDT 24 481828557 ps
T156 /workspace/coverage/default/9.sram_ctrl_partial_access.416964147 May 12 12:58:46 PM PDT 24 May 12 12:58:52 PM PDT 24 265901061 ps
T123 /workspace/coverage/default/42.sram_ctrl_executable.898970618 May 12 12:59:55 PM PDT 24 May 12 01:14:35 PM PDT 24 11646672514 ps
T124 /workspace/coverage/default/47.sram_ctrl_executable.4061106110 May 12 01:00:23 PM PDT 24 May 12 01:11:56 PM PDT 24 3489562849 ps
T89 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.389044737 May 12 12:59:27 PM PDT 24 May 12 01:02:59 PM PDT 24 14085164030 ps
T90 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2585188922 May 12 12:59:48 PM PDT 24 May 12 01:02:37 PM PDT 24 3659016715 ps
T147 /workspace/coverage/default/43.sram_ctrl_partial_access.3317746258 May 12 12:59:59 PM PDT 24 May 12 01:00:08 PM PDT 24 1715899717 ps
T53 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1485367357 May 12 12:59:04 PM PDT 24 May 12 12:59:07 PM PDT 24 177321328 ps
T69 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1823731057 May 12 12:59:34 PM PDT 24 May 12 12:59:40 PM PDT 24 70257658 ps
T157 /workspace/coverage/default/10.sram_ctrl_smoke.4000521173 May 12 12:58:46 PM PDT 24 May 12 12:59:01 PM PDT 24 252085076 ps
T158 /workspace/coverage/default/7.sram_ctrl_max_throughput.1218069182 May 12 12:58:20 PM PDT 24 May 12 12:59:00 PM PDT 24 451730616 ps
T126 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2467242048 May 12 12:58:55 PM PDT 24 May 12 01:05:38 PM PDT 24 19106779855 ps
T30 /workspace/coverage/default/25.sram_ctrl_ram_cfg.4235603850 May 12 12:59:11 PM PDT 24 May 12 12:59:12 PM PDT 24 80156597 ps
T159 /workspace/coverage/default/3.sram_ctrl_smoke.1852427730 May 12 12:58:09 PM PDT 24 May 12 12:58:26 PM PDT 24 654410522 ps
T40 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3401408779 May 12 12:58:43 PM PDT 24 May 12 01:03:14 PM PDT 24 3795084687 ps
T142 /workspace/coverage/default/47.sram_ctrl_multiple_keys.412263238 May 12 01:00:19 PM PDT 24 May 12 01:10:41 PM PDT 24 22991923615 ps
T145 /workspace/coverage/default/28.sram_ctrl_multiple_keys.1180448604 May 12 12:59:03 PM PDT 24 May 12 01:05:29 PM PDT 24 27490525113 ps
T141 /workspace/coverage/default/4.sram_ctrl_max_throughput.1670027927 May 12 12:58:13 PM PDT 24 May 12 12:59:28 PM PDT 24 137494333 ps
T148 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1575725483 May 12 12:59:58 PM PDT 24 May 12 01:05:31 PM PDT 24 36694881558 ps
T41 /workspace/coverage/default/42.sram_ctrl_regwen.1317137553 May 12 12:59:55 PM PDT 24 May 12 01:16:23 PM PDT 24 62189293285 ps
T140 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.4245412154 May 12 01:00:10 PM PDT 24 May 12 01:05:09 PM PDT 24 3102036394 ps
T132 /workspace/coverage/default/38.sram_ctrl_executable.2689879365 May 12 12:59:46 PM PDT 24 May 12 01:11:16 PM PDT 24 34111940964 ps
T160 /workspace/coverage/default/31.sram_ctrl_multiple_keys.3745756059 May 12 12:59:13 PM PDT 24 May 12 01:03:51 PM PDT 24 16140160578 ps
T70 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.315753631 May 12 01:00:32 PM PDT 24 May 12 01:08:34 PM PDT 24 2238298958 ps
T161 /workspace/coverage/default/7.sram_ctrl_regwen.1033294330 May 12 12:58:09 PM PDT 24 May 12 01:12:12 PM PDT 24 50415654536 ps
T139 /workspace/coverage/default/6.sram_ctrl_multiple_keys.2156894356 May 12 12:58:08 PM PDT 24 May 12 01:13:38 PM PDT 24 8580018600 ps
T125 /workspace/coverage/default/6.sram_ctrl_executable.1745281883 May 12 12:58:34 PM PDT 24 May 12 01:18:47 PM PDT 24 7610300694 ps
T71 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.773191205 May 12 12:58:42 PM PDT 24 May 12 01:06:36 PM PDT 24 12344505765 ps
T162 /workspace/coverage/default/49.sram_ctrl_partial_access.2712465997 May 12 01:00:31 PM PDT 24 May 12 01:00:57 PM PDT 24 320210071 ps
T133 /workspace/coverage/default/31.sram_ctrl_lc_escalation.4022547942 May 12 12:59:23 PM PDT 24 May 12 12:59:26 PM PDT 24 158923363 ps
T72 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2242769724 May 12 12:58:45 PM PDT 24 May 12 01:19:52 PM PDT 24 7837133581 ps
T163 /workspace/coverage/default/24.sram_ctrl_bijection.2141495083 May 12 12:59:00 PM PDT 24 May 12 12:59:16 PM PDT 24 789920924 ps
T26 /workspace/coverage/default/16.sram_ctrl_alert_test.1175995135 May 12 12:58:43 PM PDT 24 May 12 12:58:44 PM PDT 24 13145990 ps
T164 /workspace/coverage/default/23.sram_ctrl_max_throughput.2103761389 May 12 12:58:59 PM PDT 24 May 12 12:59:02 PM PDT 24 75602340 ps
T165 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3695472524 May 12 12:58:53 PM PDT 24 May 12 01:05:31 PM PDT 24 22778529777 ps
T73 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1601815061 May 12 12:58:49 PM PDT 24 May 12 01:01:15 PM PDT 24 2369984645 ps
T166 /workspace/coverage/default/31.sram_ctrl_ram_cfg.3835563272 May 12 12:59:16 PM PDT 24 May 12 12:59:17 PM PDT 24 144466084 ps
T144 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1284290195 May 12 12:58:58 PM PDT 24 May 12 01:13:47 PM PDT 24 37588587586 ps
T131 /workspace/coverage/default/46.sram_ctrl_multiple_keys.2464710314 May 12 01:00:18 PM PDT 24 May 12 01:12:24 PM PDT 24 17666356247 ps
T138 /workspace/coverage/default/10.sram_ctrl_ram_cfg.1642055523 May 12 12:58:49 PM PDT 24 May 12 12:58:50 PM PDT 24 127310192 ps
T137 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2853628396 May 12 12:58:46 PM PDT 24 May 12 01:04:55 PM PDT 24 48069634735 ps
T122 /workspace/coverage/default/5.sram_ctrl_stress_all.210333088 May 12 12:58:12 PM PDT 24 May 12 01:22:51 PM PDT 24 175995347408 ps
T42 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3905533497 May 12 01:00:20 PM PDT 24 May 12 01:00:27 PM PDT 24 447765444 ps
T103 /workspace/coverage/default/43.sram_ctrl_multiple_keys.1061478295 May 12 01:00:01 PM PDT 24 May 12 01:08:57 PM PDT 24 2971836699 ps
T104 /workspace/coverage/default/19.sram_ctrl_regwen.386400542 May 12 12:59:00 PM PDT 24 May 12 01:11:57 PM PDT 24 54998294945 ps
T105 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2892899251 May 12 12:59:02 PM PDT 24 May 12 12:59:07 PM PDT 24 97838825 ps
T106 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3960463945 May 12 12:58:39 PM PDT 24 May 12 01:04:20 PM PDT 24 198605374937 ps
T28 /workspace/coverage/default/42.sram_ctrl_stress_all.2921084159 May 12 01:00:00 PM PDT 24 May 12 01:08:05 PM PDT 24 21433780428 ps
T107 /workspace/coverage/default/16.sram_ctrl_executable.2768559820 May 12 12:58:41 PM PDT 24 May 12 01:08:17 PM PDT 24 11637948344 ps
T43 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2955388418 May 12 12:58:57 PM PDT 24 May 12 01:05:58 PM PDT 24 1987375618 ps
T108 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2961030488 May 12 12:59:47 PM PDT 24 May 12 01:00:42 PM PDT 24 211156941 ps
T74 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3514233218 May 12 12:59:14 PM PDT 24 May 12 01:08:39 PM PDT 24 2005330845 ps
T167 /workspace/coverage/default/37.sram_ctrl_ram_cfg.2970093847 May 12 12:59:39 PM PDT 24 May 12 12:59:40 PM PDT 24 92544635 ps
T168 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1838129788 May 12 12:59:45 PM PDT 24 May 12 01:02:53 PM PDT 24 23274521363 ps
T169 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.536596617 May 12 12:59:47 PM PDT 24 May 12 01:01:33 PM PDT 24 1136713837 ps
T146 /workspace/coverage/default/38.sram_ctrl_lc_escalation.3693348313 May 12 12:59:51 PM PDT 24 May 12 01:00:00 PM PDT 24 2960621112 ps
T170 /workspace/coverage/default/21.sram_ctrl_regwen.3507809032 May 12 12:58:53 PM PDT 24 May 12 01:07:49 PM PDT 24 12719235305 ps
T171 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3445820394 May 12 01:00:27 PM PDT 24 May 12 01:04:35 PM PDT 24 17658554009 ps
T172 /workspace/coverage/default/38.sram_ctrl_max_throughput.177606047 May 12 12:59:46 PM PDT 24 May 12 01:02:10 PM PDT 24 911391351 ps
T173 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1685669883 May 12 01:00:19 PM PDT 24 May 12 01:03:11 PM PDT 24 1767139923 ps
T174 /workspace/coverage/default/23.sram_ctrl_ram_cfg.1426421651 May 12 12:58:59 PM PDT 24 May 12 12:59:00 PM PDT 24 141339078 ps
T175 /workspace/coverage/default/49.sram_ctrl_ram_cfg.3700769028 May 12 01:00:35 PM PDT 24 May 12 01:00:36 PM PDT 24 30628200 ps
T176 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1928482311 May 12 01:00:13 PM PDT 24 May 12 01:12:30 PM PDT 24 13657487624 ps
T130 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3757325018 May 12 12:58:07 PM PDT 24 May 12 01:06:29 PM PDT 24 12040376364 ps
T177 /workspace/coverage/default/2.sram_ctrl_ram_cfg.343152394 May 12 12:58:20 PM PDT 24 May 12 12:58:22 PM PDT 24 44115893 ps
T178 /workspace/coverage/default/9.sram_ctrl_alert_test.365004605 May 12 12:58:30 PM PDT 24 May 12 12:58:31 PM PDT 24 131379816 ps
T179 /workspace/coverage/default/25.sram_ctrl_smoke.1413667450 May 12 12:59:05 PM PDT 24 May 12 12:59:20 PM PDT 24 207759416 ps
T180 /workspace/coverage/default/13.sram_ctrl_max_throughput.3781072503 May 12 12:58:37 PM PDT 24 May 12 12:59:20 PM PDT 24 110581114 ps
T181 /workspace/coverage/default/2.sram_ctrl_lc_escalation.1122921494 May 12 12:58:20 PM PDT 24 May 12 12:58:31 PM PDT 24 7357476355 ps
T44 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1511034205 May 12 12:58:07 PM PDT 24 May 12 01:05:13 PM PDT 24 1893521420 ps
T182 /workspace/coverage/default/43.sram_ctrl_smoke.641633339 May 12 12:59:59 PM PDT 24 May 12 01:00:02 PM PDT 24 65654119 ps
T183 /workspace/coverage/default/19.sram_ctrl_bijection.2578831930 May 12 12:58:51 PM PDT 24 May 12 12:59:30 PM PDT 24 864795632 ps
T184 /workspace/coverage/default/43.sram_ctrl_max_throughput.2248809953 May 12 12:59:57 PM PDT 24 May 12 01:01:48 PM PDT 24 239988127 ps
T185 /workspace/coverage/default/14.sram_ctrl_multiple_keys.1012926238 May 12 12:58:38 PM PDT 24 May 12 01:07:47 PM PDT 24 7478511089 ps
T186 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.496225502 May 12 12:58:49 PM PDT 24 May 12 12:58:58 PM PDT 24 482040387 ps
T187 /workspace/coverage/default/2.sram_ctrl_executable.2739392882 May 12 12:58:08 PM PDT 24 May 12 01:05:41 PM PDT 24 13714641224 ps
T188 /workspace/coverage/default/37.sram_ctrl_alert_test.2599664810 May 12 12:59:39 PM PDT 24 May 12 12:59:41 PM PDT 24 23349813 ps
T22 /workspace/coverage/default/3.sram_ctrl_sec_cm.2553505973 May 12 12:58:13 PM PDT 24 May 12 12:58:18 PM PDT 24 658377414 ps
T45 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2911044930 May 12 12:58:12 PM PDT 24 May 12 01:00:00 PM PDT 24 3141190258 ps
T189 /workspace/coverage/default/44.sram_ctrl_mem_walk.1533608779 May 12 01:00:15 PM PDT 24 May 12 01:00:20 PM PDT 24 338301318 ps
T190 /workspace/coverage/default/4.sram_ctrl_regwen.3192566630 May 12 12:58:16 PM PDT 24 May 12 01:17:58 PM PDT 24 6787061202 ps
T46 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3587181048 May 12 01:00:15 PM PDT 24 May 12 01:01:59 PM PDT 24 2268451400 ps
T191 /workspace/coverage/default/33.sram_ctrl_multiple_keys.320672503 May 12 12:59:24 PM PDT 24 May 12 01:16:25 PM PDT 24 6619363300 ps
T192 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3707135484 May 12 12:59:01 PM PDT 24 May 12 01:07:51 PM PDT 24 1831612130 ps
T193 /workspace/coverage/default/40.sram_ctrl_stress_all.3355020757 May 12 12:59:53 PM PDT 24 May 12 01:27:34 PM PDT 24 40730930193 ps
T194 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2884042131 May 12 12:58:28 PM PDT 24 May 12 01:01:15 PM PDT 24 9381830635 ps
T195 /workspace/coverage/default/15.sram_ctrl_mem_walk.4049340955 May 12 12:58:44 PM PDT 24 May 12 12:58:49 PM PDT 24 151723736 ps
T121 /workspace/coverage/default/17.sram_ctrl_executable.1918896226 May 12 12:58:48 PM PDT 24 May 12 01:01:36 PM PDT 24 5355154714 ps
T196 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.700401613 May 12 12:59:05 PM PDT 24 May 12 12:59:12 PM PDT 24 620975072 ps
T127 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3007573911 May 12 12:58:16 PM PDT 24 May 12 01:06:19 PM PDT 24 45430463753 ps
T197 /workspace/coverage/default/36.sram_ctrl_smoke.916087514 May 12 12:59:34 PM PDT 24 May 12 01:01:59 PM PDT 24 429662141 ps
T198 /workspace/coverage/default/40.sram_ctrl_regwen.3501768919 May 12 12:59:50 PM PDT 24 May 12 01:14:51 PM PDT 24 9871325621 ps
T199 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.891042359 May 12 12:59:04 PM PDT 24 May 12 01:14:58 PM PDT 24 3063577780 ps
T200 /workspace/coverage/default/0.sram_ctrl_executable.2433628165 May 12 12:58:11 PM PDT 24 May 12 01:06:00 PM PDT 24 52965603510 ps
T201 /workspace/coverage/default/27.sram_ctrl_mem_walk.4221622015 May 12 12:59:06 PM PDT 24 May 12 12:59:15 PM PDT 24 140139595 ps
T202 /workspace/coverage/default/40.sram_ctrl_partial_access.3826422612 May 12 12:59:47 PM PDT 24 May 12 01:00:05 PM PDT 24 2724923315 ps
T203 /workspace/coverage/default/24.sram_ctrl_ram_cfg.1434080915 May 12 12:59:02 PM PDT 24 May 12 12:59:05 PM PDT 24 61044144 ps
T204 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.108417458 May 12 12:59:09 PM PDT 24 May 12 12:59:15 PM PDT 24 153489745 ps
T205 /workspace/coverage/default/15.sram_ctrl_executable.2648942478 May 12 12:58:47 PM PDT 24 May 12 01:02:41 PM PDT 24 2622926515 ps
T206 /workspace/coverage/default/4.sram_ctrl_executable.2475796721 May 12 12:58:26 PM PDT 24 May 12 01:00:28 PM PDT 24 769464859 ps
T207 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.205192246 May 12 12:58:33 PM PDT 24 May 12 12:58:51 PM PDT 24 169758811 ps
T208 /workspace/coverage/default/32.sram_ctrl_max_throughput.692860428 May 12 12:59:21 PM PDT 24 May 12 01:00:57 PM PDT 24 407632355 ps
T209 /workspace/coverage/default/35.sram_ctrl_mem_walk.4130071324 May 12 12:59:36 PM PDT 24 May 12 12:59:48 PM PDT 24 1183048703 ps
T210 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.605723096 May 12 12:59:02 PM PDT 24 May 12 12:59:09 PM PDT 24 2687086040 ps
T211 /workspace/coverage/default/33.sram_ctrl_regwen.3329364528 May 12 12:59:28 PM PDT 24 May 12 01:22:02 PM PDT 24 20421786485 ps
T212 /workspace/coverage/default/13.sram_ctrl_ram_cfg.3604923462 May 12 12:58:34 PM PDT 24 May 12 12:58:36 PM PDT 24 83314650 ps
T213 /workspace/coverage/default/13.sram_ctrl_mem_walk.1709060518 May 12 12:58:34 PM PDT 24 May 12 12:58:39 PM PDT 24 87302873 ps
T214 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3451052041 May 12 12:59:29 PM PDT 24 May 12 01:19:48 PM PDT 24 17996177160 ps
T215 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1298229317 May 12 12:59:02 PM PDT 24 May 12 12:59:06 PM PDT 24 582444234 ps
T216 /workspace/coverage/default/44.sram_ctrl_executable.3077064813 May 12 01:00:15 PM PDT 24 May 12 01:04:05 PM PDT 24 7347426416 ps
T217 /workspace/coverage/default/25.sram_ctrl_bijection.897109300 May 12 12:59:03 PM PDT 24 May 12 12:59:40 PM PDT 24 2217622006 ps
T218 /workspace/coverage/default/10.sram_ctrl_lc_escalation.683843971 May 12 12:58:42 PM PDT 24 May 12 12:58:53 PM PDT 24 5332285798 ps
T219 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.463897214 May 12 12:58:55 PM PDT 24 May 12 12:58:59 PM PDT 24 104180118 ps
T220 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.860225497 May 12 01:00:31 PM PDT 24 May 12 01:00:36 PM PDT 24 152781621 ps
T221 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3109526204 May 12 12:59:57 PM PDT 24 May 12 01:04:28 PM PDT 24 10823058785 ps
T222 /workspace/coverage/default/11.sram_ctrl_regwen.3279185983 May 12 12:58:43 PM PDT 24 May 12 01:21:49 PM PDT 24 30700503102 ps
T47 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3332029633 May 12 12:58:45 PM PDT 24 May 12 12:59:40 PM PDT 24 1940253459 ps
T223 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2667794523 May 12 12:58:43 PM PDT 24 May 12 12:59:12 PM PDT 24 518415996 ps
T224 /workspace/coverage/default/35.sram_ctrl_executable.3065453472 May 12 12:59:31 PM PDT 24 May 12 01:24:44 PM PDT 24 63487604713 ps
T128 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.369715639 May 12 12:59:37 PM PDT 24 May 12 01:04:41 PM PDT 24 13638514053 ps
T225 /workspace/coverage/default/23.sram_ctrl_executable.927466991 May 12 12:59:09 PM PDT 24 May 12 12:59:20 PM PDT 24 1377472480 ps
T226 /workspace/coverage/default/32.sram_ctrl_executable.3329697253 May 12 12:59:24 PM PDT 24 May 12 01:05:35 PM PDT 24 45373548831 ps
T227 /workspace/coverage/default/4.sram_ctrl_mem_walk.996399852 May 12 12:58:25 PM PDT 24 May 12 12:58:31 PM PDT 24 894006434 ps
T228 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1499724779 May 12 12:58:20 PM PDT 24 May 12 01:03:17 PM PDT 24 3236472330 ps
T48 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2068450033 May 12 12:58:40 PM PDT 24 May 12 01:01:28 PM PDT 24 1711585489 ps
T229 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2487643651 May 12 12:58:59 PM PDT 24 May 12 12:59:01 PM PDT 24 29282884 ps
T230 /workspace/coverage/default/22.sram_ctrl_ram_cfg.3570974672 May 12 12:58:55 PM PDT 24 May 12 12:58:57 PM PDT 24 77996643 ps
T231 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1986650644 May 12 12:59:34 PM PDT 24 May 12 01:03:26 PM PDT 24 9884600433 ps
T232 /workspace/coverage/default/40.sram_ctrl_ram_cfg.4281053181 May 12 12:59:46 PM PDT 24 May 12 12:59:47 PM PDT 24 34539102 ps
T233 /workspace/coverage/default/48.sram_ctrl_partial_access.3534298012 May 12 01:00:26 PM PDT 24 May 12 01:00:42 PM PDT 24 830612721 ps
T234 /workspace/coverage/default/36.sram_ctrl_alert_test.3335965718 May 12 12:59:39 PM PDT 24 May 12 12:59:40 PM PDT 24 40804090 ps
T235 /workspace/coverage/default/28.sram_ctrl_executable.641758837 May 12 12:59:02 PM PDT 24 May 12 01:08:42 PM PDT 24 1219849848 ps
T236 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3396969227 May 12 12:59:37 PM PDT 24 May 12 01:00:52 PM PDT 24 121394964 ps
T237 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1882090908 May 12 12:58:46 PM PDT 24 May 12 12:58:55 PM PDT 24 500445355 ps
T238 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2713482482 May 12 12:58:10 PM PDT 24 May 12 12:58:15 PM PDT 24 265050405 ps
T239 /workspace/coverage/default/21.sram_ctrl_mem_walk.1166537802 May 12 12:58:56 PM PDT 24 May 12 12:59:01 PM PDT 24 141943261 ps
T240 /workspace/coverage/default/15.sram_ctrl_multiple_keys.1049915597 May 12 12:58:47 PM PDT 24 May 12 01:01:33 PM PDT 24 5725854160 ps
T241 /workspace/coverage/default/23.sram_ctrl_bijection.1935673864 May 12 12:59:09 PM PDT 24 May 12 01:00:21 PM PDT 24 3081433241 ps
T242 /workspace/coverage/default/28.sram_ctrl_regwen.2829867411 May 12 12:59:05 PM PDT 24 May 12 01:25:44 PM PDT 24 95651070834 ps
T243 /workspace/coverage/default/32.sram_ctrl_ram_cfg.555581311 May 12 12:59:23 PM PDT 24 May 12 12:59:24 PM PDT 24 32443322 ps
T244 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.4162431577 May 12 12:58:08 PM PDT 24 May 12 01:01:49 PM PDT 24 4588298134 ps
T245 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1963874957 May 12 01:00:19 PM PDT 24 May 12 01:05:09 PM PDT 24 3581238174 ps
T246 /workspace/coverage/default/23.sram_ctrl_smoke.3371758426 May 12 12:59:06 PM PDT 24 May 12 12:59:25 PM PDT 24 139361425 ps
T247 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.756790337 May 12 12:58:29 PM PDT 24 May 12 12:58:35 PM PDT 24 341573434 ps
T248 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2234875042 May 12 12:59:04 PM PDT 24 May 12 01:01:45 PM PDT 24 1597457895 ps
T249 /workspace/coverage/default/4.sram_ctrl_stress_all.3483293953 May 12 12:58:19 PM PDT 24 May 12 01:51:01 PM PDT 24 10030641179 ps
T75 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3741550770 May 12 12:59:29 PM PDT 24 May 12 12:59:34 PM PDT 24 167489890 ps
T250 /workspace/coverage/default/17.sram_ctrl_bijection.3279218973 May 12 12:58:57 PM PDT 24 May 12 12:59:18 PM PDT 24 10618973613 ps
T251 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2836278002 May 12 12:58:09 PM PDT 24 May 12 12:58:16 PM PDT 24 68216885 ps
T252 /workspace/coverage/default/18.sram_ctrl_max_throughput.1616095985 May 12 12:58:49 PM PDT 24 May 12 01:00:30 PM PDT 24 491742945 ps
T253 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.37455389 May 12 01:00:10 PM PDT 24 May 12 01:14:01 PM PDT 24 8825427715 ps
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T255 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3387421156 May 12 12:59:47 PM PDT 24 May 12 12:59:51 PM PDT 24 94894434 ps
T256 /workspace/coverage/default/25.sram_ctrl_partial_access.830200752 May 12 12:59:04 PM PDT 24 May 12 12:59:11 PM PDT 24 246091841 ps
T257 /workspace/coverage/default/25.sram_ctrl_alert_test.3359883394 May 12 12:59:02 PM PDT 24 May 12 12:59:04 PM PDT 24 112678407 ps
T258 /workspace/coverage/default/41.sram_ctrl_partial_access.1152578359 May 12 12:59:51 PM PDT 24 May 12 01:00:18 PM PDT 24 3332518204 ps
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T266 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3989911118 May 12 12:59:04 PM PDT 24 May 12 12:59:11 PM PDT 24 955451391 ps
T267 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.564659780 May 12 12:58:07 PM PDT 24 May 12 12:59:01 PM PDT 24 443912425 ps
T268 /workspace/coverage/default/5.sram_ctrl_regwen.3562200718 May 12 12:58:18 PM PDT 24 May 12 01:15:49 PM PDT 24 12423689397 ps
T269 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2622372689 May 12 12:58:41 PM PDT 24 May 12 12:58:48 PM PDT 24 1116007563 ps
T270 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3149031936 May 12 12:58:52 PM PDT 24 May 12 01:03:56 PM PDT 24 15952612976 ps
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T274 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1000818681 May 12 12:58:42 PM PDT 24 May 12 01:03:45 PM PDT 24 4425201642 ps
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T280 /workspace/coverage/default/24.sram_ctrl_partial_access.1338769260 May 12 12:59:01 PM PDT 24 May 12 12:59:06 PM PDT 24 77656858 ps
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T282 /workspace/coverage/default/27.sram_ctrl_partial_access.3170486674 May 12 12:59:04 PM PDT 24 May 12 12:59:13 PM PDT 24 84363827 ps
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T284 /workspace/coverage/default/37.sram_ctrl_partial_access.138568590 May 12 12:59:45 PM PDT 24 May 12 12:59:51 PM PDT 24 507097439 ps
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T290 /workspace/coverage/default/4.sram_ctrl_partial_access.4260708657 May 12 12:58:17 PM PDT 24 May 12 12:58:58 PM PDT 24 585536650 ps
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T292 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3421748896 May 12 12:59:39 PM PDT 24 May 12 01:15:49 PM PDT 24 2466504370 ps
T293 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2928596111 May 12 12:58:28 PM PDT 24 May 12 01:01:04 PM PDT 24 811599367 ps
T294 /workspace/coverage/default/1.sram_ctrl_max_throughput.2867128449 May 12 12:58:16 PM PDT 24 May 12 12:59:00 PM PDT 24 199229444 ps
T295 /workspace/coverage/default/49.sram_ctrl_mem_walk.3965455389 May 12 01:00:34 PM PDT 24 May 12 01:00:45 PM PDT 24 1347903024 ps
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T297 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1024020697 May 12 12:58:22 PM PDT 24 May 12 01:18:57 PM PDT 24 120549573753 ps
T298 /workspace/coverage/default/30.sram_ctrl_bijection.1186933655 May 12 12:59:11 PM PDT 24 May 12 12:59:41 PM PDT 24 1350232461 ps
T299 /workspace/coverage/default/2.sram_ctrl_partial_access.2879300990 May 12 12:58:06 PM PDT 24 May 12 12:58:09 PM PDT 24 644043128 ps
T300 /workspace/coverage/default/36.sram_ctrl_executable.2169834225 May 12 12:59:35 PM PDT 24 May 12 01:16:02 PM PDT 24 16143624390 ps
T301 /workspace/coverage/default/36.sram_ctrl_max_throughput.87032684 May 12 12:59:31 PM PDT 24 May 12 12:59:38 PM PDT 24 203426011 ps
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