Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42228900	1			T2	73150		T3	40960		T4	170506
triple_byte_access	2432154	1			T2	1535		T4	3443		T5	5
halfword_access	3654558	1			T2	2218		T4	5254		T5	6
byte_access	4878272	1			T2	2870		T4	6802		T5	8
zero_access	1229165	1			T2	713		T4	1680		T5	1

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27160408

1

T2

40328

T3

20480

T4

93912

auto[1]

27262641

1

T2

40158

T3

20480

T4

93773

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21068554	1			T2	36617		T3	20480		T4	85353
auto[0]	triple_byte_access	1211706	1			T2	808		T4	1711		T5	4
auto[0]	halfword_access	1823099	1			T2	1135		T4	2623		T5	4
auto[0]	byte_access	2437960	1			T2	1417		T4	3377		T5	2
auto[0]	zero_access	619089	1			T2	351		T4	848		T5	1
auto[1]	word_access	21160346	1			T2	36533		T3	20480		T4	85153
auto[1]	triple_byte_access	1220448	1			T2	727		T4	1732		T5	1
auto[1]	halfword_access	1831459	1			T2	1083		T4	2631		T5	2
auto[1]	byte_access	2440312	1			T2	1453		T4	3425		T5	6
auto[1]	zero_access	610076	1			T2	362		T4	832		T9	6