Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147950504	1			T1	1722		T2	792106		T3	228202
instr_valid_dis	115057461	1			T1	1722		T2	792106		T3	228202
instr_en	23113417	1			T5	90676		T16	139026		T49	135094

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11273850	1			T5	71962		T16	64256		T17	48270
sram_ifetch_valid_disable	114807020	1			T1	1722		T2	792106		T3	228202
sram_ifetch_enable	21869634	1			T5	113890		T16	163970		T17	265626

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147950504	1			T1	1722		T2	792106		T3	228202
hw_debug_en_valid_off	115795637	1			T1	1722		T2	792106		T3	228202
hw_debug_en_on	21511712	1			T5	245058		T16	109102		T17	145458

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114807020	1			T1	1722		T2	792106		T3	228202
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101362887	1			T1	1722		T2	792106		T3	228202
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9416182	1			T5	46052		T16	8304		T49	1386
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5116368	1			T17	28378		T25	37458		T49	55636
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1795844	1			T17	28378		T49	35636		T26	28900
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2335416	1			T64	57178		T30	11942		T60	36054
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4249086	1			T5	71962		T16	22888		T17	19892
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1643594	1			T5	47296		T16	7108		T17	19892
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1931602	1			T16	15780		T49	20000		T64	62064
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10054570	1			T5	108472		T16	28308		T17	89638
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4437100	1			T5	42270		T16	18118		T17	89638
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3932604	1			T5	10788		T16	88		T64	64146

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8614333	1			T5	44624		T16	114942		T49	113708
lc_exec_en	7208056	1			T5	64624		T16	57906		T17	35928
valid_exec_dis	110168953	1			T1	1722		T2	792106		T3	228202
invalid_exec_dis	33143484	1			T5	185852		T16	228226		T17	313896