Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44609579	1			T1	861		T2	360062		T3	103815
triple_byte_access	2548858	1			T2	7314		T3	2048		T4	1308
halfword_access	3823035	1			T2	10686		T3	3001		T4	1869
byte_access	5109397	1			T2	14348		T3	4181		T4	2519
zero_access	1288585	1			T2	3643		T3	1056		T4	636

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28637811

1

T1

452

T2

198156

T3

57088

auto[1]

28741643

1

T1

409

T2

197897

T3

57013

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22258620	1			T1	452		T2	180147		T3	51865
auto[0]	triple_byte_access	1271304	1			T2	3597		T3	1049		T4	653
auto[0]	halfword_access	1907017	1			T2	5404		T3	1498		T4	941
auto[0]	byte_access	2552520	1			T2	7214		T3	2123		T4	1250
auto[0]	zero_access	648350	1			T2	1794		T3	553		T4	339
auto[1]	word_access	22350959	1			T1	409		T2	179915		T3	51950
auto[1]	triple_byte_access	1277554	1			T2	3717		T3	999		T4	655
auto[1]	halfword_access	1916018	1			T2	5282		T3	1503		T4	928
auto[1]	byte_access	2556877	1			T2	7134		T3	2058		T4	1269
auto[1]	zero_access	640235	1			T2	1849		T3	503		T4	297