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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1027
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T791 /workspace/coverage/default/5.sram_ctrl_stress_all.123569861 May 19 02:05:34 PM PDT 24 May 19 02:26:07 PM PDT 24 6501748525 ps
T792 /workspace/coverage/default/47.sram_ctrl_max_throughput.3904965682 May 19 02:11:15 PM PDT 24 May 19 02:11:20 PM PDT 24 194486012 ps
T793 /workspace/coverage/default/45.sram_ctrl_multiple_keys.1939678076 May 19 02:10:27 PM PDT 24 May 19 02:23:24 PM PDT 24 17326381984 ps
T794 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1420970577 May 19 02:06:23 PM PDT 24 May 19 02:09:24 PM PDT 24 26971342113 ps
T795 /workspace/coverage/default/30.sram_ctrl_alert_test.248122782 May 19 02:07:03 PM PDT 24 May 19 02:07:04 PM PDT 24 14117525 ps
T796 /workspace/coverage/default/48.sram_ctrl_executable.1964208118 May 19 02:11:46 PM PDT 24 May 19 02:25:25 PM PDT 24 12473409450 ps
T797 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2138902680 May 19 02:07:33 PM PDT 24 May 19 02:07:38 PM PDT 24 158183686 ps
T798 /workspace/coverage/default/8.sram_ctrl_stress_all.4214428255 May 19 02:05:30 PM PDT 24 May 19 02:44:55 PM PDT 24 28372968031 ps
T799 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1305850224 May 19 02:06:26 PM PDT 24 May 19 02:06:32 PM PDT 24 246842776 ps
T800 /workspace/coverage/default/24.sram_ctrl_lc_escalation.3450136993 May 19 02:06:13 PM PDT 24 May 19 02:06:20 PM PDT 24 1569229215 ps
T801 /workspace/coverage/default/16.sram_ctrl_max_throughput.2745624750 May 19 02:05:59 PM PDT 24 May 19 02:06:32 PM PDT 24 353916680 ps
T802 /workspace/coverage/default/13.sram_ctrl_alert_test.2963065623 May 19 02:05:50 PM PDT 24 May 19 02:05:52 PM PDT 24 24972662 ps
T803 /workspace/coverage/default/26.sram_ctrl_lc_escalation.1265476368 May 19 02:06:31 PM PDT 24 May 19 02:06:38 PM PDT 24 438714626 ps
T804 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1758178083 May 19 02:11:56 PM PDT 24 May 19 02:12:24 PM PDT 24 1101918490 ps
T805 /workspace/coverage/default/14.sram_ctrl_bijection.1830606175 May 19 02:05:46 PM PDT 24 May 19 02:06:07 PM PDT 24 229091553 ps
T806 /workspace/coverage/default/42.sram_ctrl_lc_escalation.3322464907 May 19 02:09:38 PM PDT 24 May 19 02:09:46 PM PDT 24 5618721676 ps
T807 /workspace/coverage/default/17.sram_ctrl_max_throughput.265328328 May 19 02:05:37 PM PDT 24 May 19 02:07:29 PM PDT 24 132407721 ps
T808 /workspace/coverage/default/13.sram_ctrl_partial_access.368469729 May 19 02:05:50 PM PDT 24 May 19 02:06:12 PM PDT 24 4020148281 ps
T809 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3856029716 May 19 02:08:31 PM PDT 24 May 19 02:15:40 PM PDT 24 27969056332 ps
T810 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.245500555 May 19 02:10:29 PM PDT 24 May 19 02:13:47 PM PDT 24 2132754764 ps
T811 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1713077298 May 19 02:06:46 PM PDT 24 May 19 02:07:27 PM PDT 24 306424004 ps
T812 /workspace/coverage/default/32.sram_ctrl_ram_cfg.4171853765 May 19 02:07:21 PM PDT 24 May 19 02:07:22 PM PDT 24 57894393 ps
T813 /workspace/coverage/default/45.sram_ctrl_ram_cfg.849140137 May 19 02:10:38 PM PDT 24 May 19 02:10:39 PM PDT 24 93932761 ps
T814 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2993553188 May 19 02:06:12 PM PDT 24 May 19 02:08:39 PM PDT 24 1635111847 ps
T815 /workspace/coverage/default/10.sram_ctrl_lc_escalation.538172876 May 19 02:05:27 PM PDT 24 May 19 02:05:32 PM PDT 24 89199647 ps
T816 /workspace/coverage/default/5.sram_ctrl_bijection.796176366 May 19 02:05:25 PM PDT 24 May 19 02:05:51 PM PDT 24 1597339495 ps
T817 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3250054928 May 19 02:11:17 PM PDT 24 May 19 02:47:16 PM PDT 24 4283633869 ps
T818 /workspace/coverage/default/12.sram_ctrl_executable.4101831476 May 19 02:05:28 PM PDT 24 May 19 02:15:33 PM PDT 24 8145098066 ps
T819 /workspace/coverage/default/14.sram_ctrl_executable.718210793 May 19 02:05:29 PM PDT 24 May 19 02:26:45 PM PDT 24 5304598984 ps
T820 /workspace/coverage/default/16.sram_ctrl_stress_all.1775668902 May 19 02:05:45 PM PDT 24 May 19 03:09:23 PM PDT 24 30891986550 ps
T821 /workspace/coverage/default/5.sram_ctrl_partial_access.2364255125 May 19 02:05:28 PM PDT 24 May 19 02:05:45 PM PDT 24 88624913 ps
T822 /workspace/coverage/default/31.sram_ctrl_max_throughput.1161609104 May 19 02:07:07 PM PDT 24 May 19 02:07:09 PM PDT 24 51584869 ps
T823 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2821647257 May 19 02:08:46 PM PDT 24 May 19 02:13:41 PM PDT 24 25849366909 ps
T824 /workspace/coverage/default/14.sram_ctrl_smoke.849313663 May 19 02:05:43 PM PDT 24 May 19 02:05:54 PM PDT 24 178527512 ps
T825 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3108793607 May 19 02:05:56 PM PDT 24 May 19 02:09:23 PM PDT 24 4397024958 ps
T826 /workspace/coverage/default/6.sram_ctrl_partial_access.3274348550 May 19 02:05:31 PM PDT 24 May 19 02:05:38 PM PDT 24 75082326 ps
T827 /workspace/coverage/default/36.sram_ctrl_mem_walk.2755136147 May 19 02:08:04 PM PDT 24 May 19 02:08:09 PM PDT 24 765767197 ps
T828 /workspace/coverage/default/4.sram_ctrl_mem_walk.1907080685 May 19 02:05:30 PM PDT 24 May 19 02:05:46 PM PDT 24 1684675007 ps
T829 /workspace/coverage/default/44.sram_ctrl_alert_test.1922119049 May 19 02:10:23 PM PDT 24 May 19 02:10:24 PM PDT 24 27638779 ps
T830 /workspace/coverage/default/20.sram_ctrl_bijection.2299182111 May 19 02:06:04 PM PDT 24 May 19 02:06:50 PM PDT 24 1274992431 ps
T831 /workspace/coverage/default/0.sram_ctrl_partial_access.1161953512 May 19 02:05:17 PM PDT 24 May 19 02:06:02 PM PDT 24 412678213 ps
T832 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.535332421 May 19 02:05:34 PM PDT 24 May 19 02:08:57 PM PDT 24 12417333009 ps
T833 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2777394371 May 19 02:06:55 PM PDT 24 May 19 02:21:27 PM PDT 24 3070134625 ps
T834 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4078966183 May 19 02:05:38 PM PDT 24 May 19 02:13:34 PM PDT 24 40714421402 ps
T835 /workspace/coverage/default/30.sram_ctrl_stress_all.2744506749 May 19 02:07:03 PM PDT 24 May 19 03:02:09 PM PDT 24 79794356713 ps
T836 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.369010330 May 19 02:06:30 PM PDT 24 May 19 02:07:16 PM PDT 24 475830596 ps
T837 /workspace/coverage/default/36.sram_ctrl_stress_all.461617367 May 19 02:08:06 PM PDT 24 May 19 03:08:07 PM PDT 24 42621935356 ps
T838 /workspace/coverage/default/48.sram_ctrl_stress_all.2827595995 May 19 02:11:55 PM PDT 24 May 19 02:52:31 PM PDT 24 50116913019 ps
T839 /workspace/coverage/default/14.sram_ctrl_mem_walk.1453827330 May 19 02:05:52 PM PDT 24 May 19 02:05:59 PM PDT 24 882308359 ps
T840 /workspace/coverage/default/28.sram_ctrl_ram_cfg.928638578 May 19 02:06:45 PM PDT 24 May 19 02:06:46 PM PDT 24 72692294 ps
T841 /workspace/coverage/default/34.sram_ctrl_regwen.3178690645 May 19 02:07:49 PM PDT 24 May 19 02:20:16 PM PDT 24 3883792108 ps
T842 /workspace/coverage/default/30.sram_ctrl_smoke.3310746876 May 19 02:07:00 PM PDT 24 May 19 02:07:13 PM PDT 24 251295505 ps
T843 /workspace/coverage/default/41.sram_ctrl_executable.3493346353 May 19 02:09:22 PM PDT 24 May 19 02:13:45 PM PDT 24 44586304554 ps
T844 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2512637777 May 19 02:11:40 PM PDT 24 May 19 02:11:48 PM PDT 24 5076059233 ps
T845 /workspace/coverage/default/41.sram_ctrl_lc_escalation.3797083976 May 19 02:09:23 PM PDT 24 May 19 02:09:32 PM PDT 24 635137792 ps
T846 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3906424714 May 19 02:07:00 PM PDT 24 May 19 02:15:07 PM PDT 24 55301216540 ps
T847 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.239302691 May 19 02:06:05 PM PDT 24 May 19 02:09:24 PM PDT 24 2106812501 ps
T848 /workspace/coverage/default/20.sram_ctrl_smoke.3430847587 May 19 02:06:01 PM PDT 24 May 19 02:07:55 PM PDT 24 6853113465 ps
T849 /workspace/coverage/default/19.sram_ctrl_stress_all.2523669206 May 19 02:06:12 PM PDT 24 May 19 02:24:31 PM PDT 24 51561168305 ps
T850 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2880400412 May 19 02:11:03 PM PDT 24 May 19 02:11:04 PM PDT 24 41782828 ps
T851 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2621310994 May 19 02:05:30 PM PDT 24 May 19 02:05:38 PM PDT 24 98759715 ps
T852 /workspace/coverage/default/42.sram_ctrl_smoke.1444404747 May 19 02:09:26 PM PDT 24 May 19 02:10:25 PM PDT 24 830333984 ps
T853 /workspace/coverage/default/40.sram_ctrl_smoke.1687582126 May 19 02:08:55 PM PDT 24 May 19 02:10:29 PM PDT 24 688682580 ps
T854 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3801456891 May 19 02:06:39 PM PDT 24 May 19 02:15:39 PM PDT 24 5976901055 ps
T855 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3550496071 May 19 02:05:11 PM PDT 24 May 19 02:22:53 PM PDT 24 19700665342 ps
T856 /workspace/coverage/default/37.sram_ctrl_ram_cfg.1043798617 May 19 02:08:20 PM PDT 24 May 19 02:08:21 PM PDT 24 28773073 ps
T857 /workspace/coverage/default/37.sram_ctrl_alert_test.2909111511 May 19 02:08:24 PM PDT 24 May 19 02:08:25 PM PDT 24 22824976 ps
T858 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3498248681 May 19 02:05:32 PM PDT 24 May 19 02:07:48 PM PDT 24 4997934005 ps
T859 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.106815451 May 19 02:06:04 PM PDT 24 May 19 02:09:51 PM PDT 24 11808425870 ps
T860 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.342017745 May 19 02:10:40 PM PDT 24 May 19 02:10:44 PM PDT 24 402773894 ps
T861 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4246187582 May 19 02:05:30 PM PDT 24 May 19 02:12:14 PM PDT 24 15721418280 ps
T862 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3327929270 May 19 02:08:16 PM PDT 24 May 19 02:08:18 PM PDT 24 678243276 ps
T863 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1526952846 May 19 02:05:50 PM PDT 24 May 19 02:05:55 PM PDT 24 545799313 ps
T864 /workspace/coverage/default/1.sram_ctrl_multiple_keys.963258490 May 19 02:05:23 PM PDT 24 May 19 02:19:15 PM PDT 24 17590035982 ps
T865 /workspace/coverage/default/41.sram_ctrl_mem_walk.3128066558 May 19 02:09:25 PM PDT 24 May 19 02:09:30 PM PDT 24 75733979 ps
T866 /workspace/coverage/default/10.sram_ctrl_executable.4288362191 May 19 02:05:52 PM PDT 24 May 19 02:13:16 PM PDT 24 20368925988 ps
T867 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1233272061 May 19 02:09:32 PM PDT 24 May 19 02:15:17 PM PDT 24 13632187109 ps
T868 /workspace/coverage/default/9.sram_ctrl_lc_escalation.904783216 May 19 02:05:38 PM PDT 24 May 19 02:05:50 PM PDT 24 793453971 ps
T869 /workspace/coverage/default/8.sram_ctrl_regwen.1366171635 May 19 02:05:30 PM PDT 24 May 19 02:18:36 PM PDT 24 2602514226 ps
T870 /workspace/coverage/default/24.sram_ctrl_smoke.1611777493 May 19 02:06:18 PM PDT 24 May 19 02:08:19 PM PDT 24 495170526 ps
T871 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.351604790 May 19 02:06:02 PM PDT 24 May 19 02:10:18 PM PDT 24 5417107968 ps
T872 /workspace/coverage/default/22.sram_ctrl_executable.2726362933 May 19 02:06:10 PM PDT 24 May 19 02:11:25 PM PDT 24 23470558077 ps
T873 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3035620506 May 19 02:08:42 PM PDT 24 May 19 02:11:26 PM PDT 24 594325852 ps
T874 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1962080939 May 19 02:08:17 PM PDT 24 May 19 02:17:19 PM PDT 24 1110218308 ps
T875 /workspace/coverage/default/16.sram_ctrl_bijection.3930197927 May 19 02:06:02 PM PDT 24 May 19 02:06:52 PM PDT 24 2763406504 ps
T876 /workspace/coverage/default/31.sram_ctrl_executable.1864630825 May 19 02:07:08 PM PDT 24 May 19 02:15:46 PM PDT 24 25339500620 ps
T877 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1480815739 May 19 02:06:15 PM PDT 24 May 19 02:07:17 PM PDT 24 6782999758 ps
T878 /workspace/coverage/default/41.sram_ctrl_partial_access.2185724072 May 19 02:09:16 PM PDT 24 May 19 02:10:32 PM PDT 24 1561890502 ps
T879 /workspace/coverage/default/8.sram_ctrl_executable.3709376326 May 19 02:05:45 PM PDT 24 May 19 02:14:33 PM PDT 24 49404815412 ps
T880 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2548692496 May 19 02:11:13 PM PDT 24 May 19 02:17:18 PM PDT 24 57880021911 ps
T881 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2991901662 May 19 02:05:29 PM PDT 24 May 19 02:09:00 PM PDT 24 2552058093 ps
T882 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1897536665 May 19 02:06:21 PM PDT 24 May 19 02:06:25 PM PDT 24 168652898 ps
T883 /workspace/coverage/default/7.sram_ctrl_max_throughput.1727409386 May 19 02:05:26 PM PDT 24 May 19 02:05:33 PM PDT 24 360136856 ps
T884 /workspace/coverage/default/10.sram_ctrl_regwen.2884283386 May 19 02:05:51 PM PDT 24 May 19 02:09:51 PM PDT 24 7978799406 ps
T885 /workspace/coverage/default/25.sram_ctrl_smoke.2606622594 May 19 02:06:29 PM PDT 24 May 19 02:06:33 PM PDT 24 278694017 ps
T886 /workspace/coverage/default/12.sram_ctrl_smoke.50105102 May 19 02:05:56 PM PDT 24 May 19 02:05:58 PM PDT 24 33522976 ps
T887 /workspace/coverage/default/44.sram_ctrl_partial_access.4211520771 May 19 02:10:09 PM PDT 24 May 19 02:13:00 PM PDT 24 777262398 ps
T888 /workspace/coverage/default/35.sram_ctrl_ram_cfg.3425336690 May 19 02:07:49 PM PDT 24 May 19 02:07:52 PM PDT 24 84863427 ps
T889 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.702580448 May 19 02:06:11 PM PDT 24 May 19 02:28:31 PM PDT 24 8022270201 ps
T890 /workspace/coverage/default/11.sram_ctrl_smoke.1116536488 May 19 02:06:03 PM PDT 24 May 19 02:06:19 PM PDT 24 5016169277 ps
T891 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1014142547 May 19 02:06:28 PM PDT 24 May 19 02:06:33 PM PDT 24 316384991 ps
T892 /workspace/coverage/default/26.sram_ctrl_partial_access.737106921 May 19 02:06:32 PM PDT 24 May 19 02:06:55 PM PDT 24 4293044687 ps
T893 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2536116943 May 19 02:09:31 PM PDT 24 May 19 02:11:35 PM PDT 24 158039510 ps
T894 /workspace/coverage/default/8.sram_ctrl_mem_walk.3266514148 May 19 02:05:32 PM PDT 24 May 19 02:05:42 PM PDT 24 78175456 ps
T895 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.889063577 May 19 02:05:53 PM PDT 24 May 19 02:10:00 PM PDT 24 3608990406 ps
T896 /workspace/coverage/default/41.sram_ctrl_regwen.452527900 May 19 02:09:24 PM PDT 24 May 19 02:20:57 PM PDT 24 7185218685 ps
T897 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1089510402 May 19 02:07:30 PM PDT 24 May 19 02:15:31 PM PDT 24 2777519193 ps
T898 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2274735422 May 19 02:06:33 PM PDT 24 May 19 02:20:47 PM PDT 24 2620713269 ps
T899 /workspace/coverage/default/40.sram_ctrl_regwen.464163070 May 19 02:09:03 PM PDT 24 May 19 02:33:19 PM PDT 24 21618510220 ps
T900 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1630123048 May 19 02:06:17 PM PDT 24 May 19 02:06:23 PM PDT 24 171056306 ps
T901 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2691958335 May 19 02:10:35 PM PDT 24 May 19 02:12:35 PM PDT 24 525048990 ps
T902 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1808340913 May 19 02:06:00 PM PDT 24 May 19 02:20:34 PM PDT 24 4085827795 ps
T903 /workspace/coverage/default/10.sram_ctrl_ram_cfg.2185754299 May 19 02:05:33 PM PDT 24 May 19 02:05:39 PM PDT 24 49485780 ps
T904 /workspace/coverage/default/19.sram_ctrl_bijection.1561147837 May 19 02:06:02 PM PDT 24 May 19 02:06:24 PM PDT 24 370705083 ps
T905 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3231442014 May 19 02:06:20 PM PDT 24 May 19 02:07:19 PM PDT 24 4904886494 ps
T906 /workspace/coverage/default/45.sram_ctrl_alert_test.83178893 May 19 02:10:43 PM PDT 24 May 19 02:10:44 PM PDT 24 13886428 ps
T907 /workspace/coverage/default/31.sram_ctrl_stress_all.392844091 May 19 02:07:08 PM PDT 24 May 19 02:29:52 PM PDT 24 70149479846 ps
T908 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1471606193 May 19 02:07:09 PM PDT 24 May 19 02:07:14 PM PDT 24 1240816098 ps
T909 /workspace/coverage/default/30.sram_ctrl_lc_escalation.1724110387 May 19 02:06:58 PM PDT 24 May 19 02:07:07 PM PDT 24 971999724 ps
T910 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1954657875 May 19 02:05:22 PM PDT 24 May 19 02:09:32 PM PDT 24 9419841479 ps
T911 /workspace/coverage/default/25.sram_ctrl_partial_access.3234391313 May 19 02:06:24 PM PDT 24 May 19 02:06:39 PM PDT 24 512950036 ps
T912 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1379738288 May 19 02:05:57 PM PDT 24 May 19 02:09:53 PM PDT 24 9980548517 ps
T913 /workspace/coverage/default/45.sram_ctrl_max_throughput.684755458 May 19 02:10:34 PM PDT 24 May 19 02:10:46 PM PDT 24 175723640 ps
T914 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3985229193 May 19 02:07:22 PM PDT 24 May 19 02:08:18 PM PDT 24 3547455377 ps
T915 /workspace/coverage/default/47.sram_ctrl_smoke.2598971563 May 19 02:11:09 PM PDT 24 May 19 02:11:14 PM PDT 24 359320440 ps
T916 /workspace/coverage/default/21.sram_ctrl_lc_escalation.681931436 May 19 02:06:25 PM PDT 24 May 19 02:06:33 PM PDT 24 575958806 ps
T917 /workspace/coverage/default/29.sram_ctrl_alert_test.3665529810 May 19 02:06:53 PM PDT 24 May 19 02:06:54 PM PDT 24 17346684 ps
T918 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2842343093 May 19 02:10:57 PM PDT 24 May 19 02:16:40 PM PDT 24 8687884034 ps
T919 /workspace/coverage/default/8.sram_ctrl_smoke.3259633654 May 19 02:06:00 PM PDT 24 May 19 02:06:13 PM PDT 24 259705773 ps
T920 /workspace/coverage/default/4.sram_ctrl_executable.3179114709 May 19 02:05:25 PM PDT 24 May 19 02:20:59 PM PDT 24 34119949088 ps
T921 /workspace/coverage/default/40.sram_ctrl_mem_walk.1229772943 May 19 02:09:03 PM PDT 24 May 19 02:09:11 PM PDT 24 288046792 ps
T922 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2057221496 May 19 02:07:07 PM PDT 24 May 19 02:12:01 PM PDT 24 18572910430 ps
T923 /workspace/coverage/default/11.sram_ctrl_max_throughput.1159236286 May 19 02:05:55 PM PDT 24 May 19 02:07:54 PM PDT 24 267162711 ps
T924 /workspace/coverage/default/28.sram_ctrl_partial_access.2776806507 May 19 02:06:41 PM PDT 24 May 19 02:06:54 PM PDT 24 1033755092 ps
T925 /workspace/coverage/default/34.sram_ctrl_executable.786261197 May 19 02:07:49 PM PDT 24 May 19 02:33:14 PM PDT 24 18454213560 ps
T926 /workspace/coverage/default/28.sram_ctrl_lc_escalation.951376753 May 19 02:06:46 PM PDT 24 May 19 02:06:53 PM PDT 24 2837868048 ps
T927 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3298719457 May 19 02:05:37 PM PDT 24 May 19 02:05:45 PM PDT 24 145457812 ps
T928 /workspace/coverage/default/7.sram_ctrl_partial_access.3501155952 May 19 02:05:34 PM PDT 24 May 19 02:06:24 PM PDT 24 887429411 ps
T929 /workspace/coverage/default/12.sram_ctrl_ram_cfg.1615118469 May 19 02:05:49 PM PDT 24 May 19 02:05:50 PM PDT 24 39270563 ps
T930 /workspace/coverage/default/4.sram_ctrl_stress_all.2661782340 May 19 02:05:23 PM PDT 24 May 19 02:28:14 PM PDT 24 33650854817 ps
T931 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2586045997 May 19 02:05:52 PM PDT 24 May 19 02:05:55 PM PDT 24 27416370 ps
T932 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.306387400 May 19 02:07:17 PM PDT 24 May 19 02:17:08 PM PDT 24 24312009911 ps
T933 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1845642574 May 19 02:11:08 PM PDT 24 May 19 02:16:07 PM PDT 24 1191856810 ps
T934 /workspace/coverage/default/12.sram_ctrl_mem_walk.3641360338 May 19 02:06:02 PM PDT 24 May 19 02:06:10 PM PDT 24 1649183993 ps
T935 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1756889606 May 19 02:06:35 PM PDT 24 May 19 02:06:36 PM PDT 24 59663327 ps
T73 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4098666734 May 19 01:53:04 PM PDT 24 May 19 01:53:05 PM PDT 24 46765290 ps
T74 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2811697429 May 19 01:53:05 PM PDT 24 May 19 01:53:07 PM PDT 24 161622959 ps
T75 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.249149365 May 19 01:53:20 PM PDT 24 May 19 01:53:24 PM PDT 24 3510230204 ps
T109 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3518627773 May 19 01:53:23 PM PDT 24 May 19 01:53:24 PM PDT 24 13291306 ps
T106 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.750807626 May 19 01:53:17 PM PDT 24 May 19 01:53:20 PM PDT 24 134682177 ps
T105 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3462910305 May 19 01:53:10 PM PDT 24 May 19 01:53:12 PM PDT 24 27786752 ps
T936 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1847155379 May 19 01:53:14 PM PDT 24 May 19 01:53:15 PM PDT 24 126761361 ps
T937 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.99494783 May 19 01:53:49 PM PDT 24 May 19 01:53:53 PM PDT 24 160909013 ps
T76 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.331856805 May 19 01:53:39 PM PDT 24 May 19 01:53:40 PM PDT 24 10585155 ps
T77 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3710852421 May 19 01:53:17 PM PDT 24 May 19 01:53:19 PM PDT 24 41135154 ps
T78 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.235293983 May 19 01:53:49 PM PDT 24 May 19 01:53:51 PM PDT 24 12757084 ps
T79 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2584721947 May 19 01:53:40 PM PDT 24 May 19 01:53:43 PM PDT 24 233866830 ps
T80 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.750354182 May 19 01:53:41 PM PDT 24 May 19 01:53:42 PM PDT 24 43358905 ps
T81 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.863807526 May 19 01:53:47 PM PDT 24 May 19 01:53:48 PM PDT 24 14137773 ps
T82 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.444576008 May 19 01:53:29 PM PDT 24 May 19 01:53:30 PM PDT 24 17186975 ps
T938 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3271930827 May 19 01:53:16 PM PDT 24 May 19 01:53:17 PM PDT 24 28924230 ps
T939 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2096798932 May 19 01:53:08 PM PDT 24 May 19 01:53:10 PM PDT 24 34092612 ps
T87 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3740533137 May 19 01:53:06 PM PDT 24 May 19 01:53:09 PM PDT 24 1848880630 ps
T107 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2179877394 May 19 01:53:14 PM PDT 24 May 19 01:53:17 PM PDT 24 2236685952 ps
T108 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.511810382 May 19 01:53:24 PM PDT 24 May 19 01:53:26 PM PDT 24 403646319 ps
T100 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1170811423 May 19 01:53:11 PM PDT 24 May 19 01:53:12 PM PDT 24 39471138 ps
T88 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3495120861 May 19 01:53:23 PM PDT 24 May 19 01:53:27 PM PDT 24 770101794 ps
T101 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1943986150 May 19 01:53:50 PM PDT 24 May 19 01:53:52 PM PDT 24 27183789 ps
T940 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1446632751 May 19 01:53:38 PM PDT 24 May 19 01:53:39 PM PDT 24 110179035 ps
T941 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1633341490 May 19 01:53:48 PM PDT 24 May 19 01:53:50 PM PDT 24 19746247 ps
T123 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2106403494 May 19 01:53:14 PM PDT 24 May 19 01:53:16 PM PDT 24 159815886 ps
T942 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2842463952 May 19 01:53:49 PM PDT 24 May 19 01:53:51 PM PDT 24 22747627 ps
T124 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1588831932 May 19 01:53:29 PM PDT 24 May 19 01:53:31 PM PDT 24 122442471 ps
T89 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1639749837 May 19 01:53:20 PM PDT 24 May 19 01:53:23 PM PDT 24 436498534 ps
T943 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.51982986 May 19 01:53:45 PM PDT 24 May 19 01:53:48 PM PDT 24 1642114105 ps
T944 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2695934510 May 19 01:53:39 PM PDT 24 May 19 01:53:40 PM PDT 24 31896189 ps
T127 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1535449435 May 19 01:53:09 PM PDT 24 May 19 01:53:11 PM PDT 24 323033340 ps
T90 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1838089496 May 19 01:53:24 PM PDT 24 May 19 01:53:26 PM PDT 24 219059005 ps
T945 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.934582067 May 19 01:53:47 PM PDT 24 May 19 01:53:50 PM PDT 24 63748023 ps
T946 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.286710507 May 19 01:53:16 PM PDT 24 May 19 01:53:19 PM PDT 24 36096688 ps
T947 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1850718018 May 19 01:53:48 PM PDT 24 May 19 01:53:50 PM PDT 24 58445557 ps
T91 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4224616270 May 19 01:53:53 PM PDT 24 May 19 01:53:58 PM PDT 24 499416502 ps
T128 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3406169470 May 19 01:53:17 PM PDT 24 May 19 01:53:20 PM PDT 24 483981613 ps
T130 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2291024640 May 19 01:53:48 PM PDT 24 May 19 01:53:53 PM PDT 24 4308155613 ps
T948 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4033310235 May 19 01:53:47 PM PDT 24 May 19 01:53:49 PM PDT 24 79069325 ps
T97 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2239613128 May 19 01:53:14 PM PDT 24 May 19 01:53:17 PM PDT 24 2278039132 ps
T129 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1689762857 May 19 01:53:50 PM PDT 24 May 19 01:53:54 PM PDT 24 216527773 ps
T949 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3297556474 May 19 01:53:31 PM PDT 24 May 19 01:53:36 PM PDT 24 116796565 ps
T950 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2089168874 May 19 01:53:09 PM PDT 24 May 19 01:53:12 PM PDT 24 213450968 ps
T951 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4142207818 May 19 01:53:08 PM PDT 24 May 19 01:53:09 PM PDT 24 178097944 ps
T952 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1953269965 May 19 01:53:51 PM PDT 24 May 19 01:53:54 PM PDT 24 46327214 ps
T953 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1088224376 May 19 01:53:33 PM PDT 24 May 19 01:53:35 PM PDT 24 212328031 ps
T954 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3701127473 May 19 01:53:01 PM PDT 24 May 19 01:53:02 PM PDT 24 72521104 ps
T955 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2805404063 May 19 01:53:37 PM PDT 24 May 19 01:53:39 PM PDT 24 169449118 ps
T956 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.668289435 May 19 01:53:09 PM PDT 24 May 19 01:53:14 PM PDT 24 230384977 ps
T957 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3048757210 May 19 01:53:34 PM PDT 24 May 19 01:53:36 PM PDT 24 107829865 ps
T958 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2092146349 May 19 01:53:15 PM PDT 24 May 19 01:53:17 PM PDT 24 109758027 ps
T959 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3605898680 May 19 01:53:16 PM PDT 24 May 19 01:53:18 PM PDT 24 125864176 ps
T960 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1617188559 May 19 01:53:47 PM PDT 24 May 19 01:53:48 PM PDT 24 51911399 ps
T961 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2764198881 May 19 01:53:18 PM PDT 24 May 19 01:53:19 PM PDT 24 74630503 ps
T962 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1972709976 May 19 01:53:33 PM PDT 24 May 19 01:53:34 PM PDT 24 46040422 ps
T963 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1919999387 May 19 01:53:40 PM PDT 24 May 19 01:53:43 PM PDT 24 3395284626 ps
T964 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.375772046 May 19 01:53:08 PM PDT 24 May 19 01:53:09 PM PDT 24 15520129 ps
T965 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3308160176 May 19 01:53:23 PM PDT 24 May 19 01:53:27 PM PDT 24 297170814 ps
T95 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3924583213 May 19 01:53:10 PM PDT 24 May 19 01:53:12 PM PDT 24 825147500 ps
T96 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2037543616 May 19 01:53:36 PM PDT 24 May 19 01:53:40 PM PDT 24 420201658 ps
T966 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1058655043 May 19 01:53:23 PM PDT 24 May 19 01:53:25 PM PDT 24 33389731 ps
T135 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3466254112 May 19 01:53:05 PM PDT 24 May 19 01:53:08 PM PDT 24 341833022 ps
T967 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2821199740 May 19 01:53:19 PM PDT 24 May 19 01:53:21 PM PDT 24 27921632 ps
T968 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1992827662 May 19 01:53:41 PM PDT 24 May 19 01:53:44 PM PDT 24 72466673 ps
T98 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1403940901 May 19 01:53:50 PM PDT 24 May 19 01:53:55 PM PDT 24 759015511 ps
T969 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1756621124 May 19 01:53:46 PM PDT 24 May 19 01:53:47 PM PDT 24 16079021 ps
T970 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1123692633 May 19 01:53:20 PM PDT 24 May 19 01:53:22 PM PDT 24 81023731 ps
T971 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3229394662 May 19 01:53:15 PM PDT 24 May 19 01:53:16 PM PDT 24 32934734 ps
T134 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.565054007 May 19 01:53:09 PM PDT 24 May 19 01:53:12 PM PDT 24 176527379 ps
T972 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2055686804 May 19 01:53:48 PM PDT 24 May 19 01:53:50 PM PDT 24 62999486 ps
T973 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3361664798 May 19 01:53:12 PM PDT 24 May 19 01:53:14 PM PDT 24 53380681 ps
T99 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1256732307 May 19 01:53:35 PM PDT 24 May 19 01:53:36 PM PDT 24 25034055 ps
T974 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1312316489 May 19 01:53:18 PM PDT 24 May 19 01:53:20 PM PDT 24 20875075 ps
T133 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3813386473 May 19 01:53:49 PM PDT 24 May 19 01:53:52 PM PDT 24 261771646 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.624300514 May 19 01:53:19 PM PDT 24 May 19 01:53:21 PM PDT 24 442371094 ps
T976 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2975048232 May 19 01:53:08 PM PDT 24 May 19 01:53:09 PM PDT 24 54927760 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4169578927 May 19 01:53:06 PM PDT 24 May 19 01:53:08 PM PDT 24 383588529 ps
T978 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2542641666 May 19 01:53:13 PM PDT 24 May 19 01:53:14 PM PDT 24 32351460 ps
T979 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2906246785 May 19 01:53:48 PM PDT 24 May 19 01:53:55 PM PDT 24 7630193300 ps
T125 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.350501790 May 19 01:53:35 PM PDT 24 May 19 01:53:38 PM PDT 24 188170445 ps
T980 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2083120700 May 19 01:53:30 PM PDT 24 May 19 01:53:35 PM PDT 24 121148991 ps
T981 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3990040646 May 19 01:53:31 PM PDT 24 May 19 01:53:34 PM PDT 24 30350571 ps
T982 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4241535337 May 19 01:53:06 PM PDT 24 May 19 01:53:08 PM PDT 24 723569119 ps
T983 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2700495497 May 19 01:53:16 PM PDT 24 May 19 01:53:18 PM PDT 24 139205595 ps
T984 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1244394381 May 19 01:53:28 PM PDT 24 May 19 01:53:29 PM PDT 24 83445369 ps
T985 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.426553590 May 19 01:53:07 PM PDT 24 May 19 01:53:10 PM PDT 24 29453736 ps
T986 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.72050976 May 19 01:53:12 PM PDT 24 May 19 01:53:15 PM PDT 24 247629202 ps
T987 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.38476781 May 19 01:53:22 PM PDT 24 May 19 01:53:25 PM PDT 24 92454057 ps
T988 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2900679729 May 19 01:53:06 PM PDT 24 May 19 01:53:07 PM PDT 24 49647752 ps
T989 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1715199891 May 19 01:53:10 PM PDT 24 May 19 01:53:12 PM PDT 24 12809551 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.963966715 May 19 01:53:07 PM PDT 24 May 19 01:53:09 PM PDT 24 14284464 ps
T991 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.936120987 May 19 01:53:49 PM PDT 24 May 19 01:53:52 PM PDT 24 58747714 ps
T126 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2654715882 May 19 01:53:34 PM PDT 24 May 19 01:53:37 PM PDT 24 263052522 ps
T992 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.631404262 May 19 01:53:07 PM PDT 24 May 19 01:53:11 PM PDT 24 1641104867 ps
T993 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2112076107 May 19 01:53:45 PM PDT 24 May 19 01:53:46 PM PDT 24 61728225 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1040022860 May 19 01:53:10 PM PDT 24 May 19 01:53:12 PM PDT 24 37623156 ps
T995 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2392528131 May 19 01:53:33 PM PDT 24 May 19 01:53:36 PM PDT 24 165925322 ps
T131 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.933765024 May 19 01:53:49 PM PDT 24 May 19 01:53:51 PM PDT 24 107654927 ps
T996 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.849545372 May 19 01:53:18 PM PDT 24 May 19 01:53:19 PM PDT 24 62172227 ps
T997 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3066911020 May 19 01:53:37 PM PDT 24 May 19 01:53:42 PM PDT 24 189817386 ps
T998 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1807560501 May 19 01:53:51 PM PDT 24 May 19 01:53:54 PM PDT 24 54586689 ps
T999 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3704722183 May 19 01:53:55 PM PDT 24 May 19 01:53:58 PM PDT 24 362711778 ps
T1000 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1957133312 May 19 01:53:44 PM PDT 24 May 19 01:53:47 PM PDT 24 3310079775 ps
T1001 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2406726544 May 19 01:53:09 PM PDT 24 May 19 01:53:17 PM PDT 24 711799901 ps
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