Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14429116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59172135

1

T1

294

T2

197087

T3

107561

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36698477	1			T1	152		T2	108563		T3	58841
values[0x0]	17008096	1			T1	98		T2	52229		T3	28850
values[0x1]	19894678	1			T1	70		T2	56051		T3	30665

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7190857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66410394

1

T1

308

T2

206911

T3

113023

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	285731	1			T3	415		T6	318		T7	287
valid_sources[0x01]	243444	1			T1	2		T3	455		T6	345
valid_sources[0x02]	276039	1			T1	1		T3	432		T6	334
valid_sources[0x03]	315604	1			T1	1		T3	422		T6	304
valid_sources[0x04]	275458	1			T1	2		T3	469		T4	139
valid_sources[0x05]	283659	1			T2	4796		T3	460		T4	61
valid_sources[0x06]	234080	1			T3	456		T4	28		T6	324
valid_sources[0x07]	260558	1			T1	2		T3	454		T6	319
valid_sources[0x08]	306853	1			T1	2		T3	439		T6	302
valid_sources[0x09]	229897	1			T3	439		T6	298		T7	374
valid_sources[0x0a]	325566	1			T1	2		T3	454		T4	35
valid_sources[0x0b]	253824	1			T1	2		T3	465		T6	322
valid_sources[0x0c]	306145	1			T1	3		T3	494		T6	336
valid_sources[0x0d]	301474	1			T1	1		T3	457		T6	329
valid_sources[0x0e]	272487	1			T1	1		T3	510		T6	325
valid_sources[0x0f]	298271	1			T1	3		T3	469		T6	310
valid_sources[0x10]	302671	1			T3	477		T6	294		T7	354
valid_sources[0x11]	337742	1			T1	2		T3	472		T6	340
valid_sources[0x12]	340224	1			T3	452		T6	306		T7	336
valid_sources[0x13]	292191	1			T1	2		T3	473		T6	297
valid_sources[0x14]	336827	1			T1	1		T3	457		T6	279
valid_sources[0x15]	306707	1			T1	1		T3	467		T4	81
valid_sources[0x16]	290774	1			T2	3109		T3	454		T6	316
valid_sources[0x17]	407867	1			T1	2		T3	470		T6	311
valid_sources[0x18]	291857	1			T1	2		T3	512		T6	328
valid_sources[0x19]	270380	1			T1	1		T3	445		T6	308
valid_sources[0x1a]	299988	1			T1	2		T3	451		T6	320
valid_sources[0x1b]	265920	1			T3	493		T6	329		T7	320
valid_sources[0x1c]	271977	1			T3	466		T6	326		T7	270
valid_sources[0x1d]	304027	1			T1	1		T3	483		T4	5
valid_sources[0x1e]	403047	1			T1	3		T3	487		T6	287
valid_sources[0x1f]	313397	1			T1	4		T3	454		T4	41
valid_sources[0x20]	306891	1			T1	3		T3	411		T6	337
valid_sources[0x21]	289952	1			T3	478		T6	355		T7	313
valid_sources[0x22]	303491	1			T1	1		T3	441		T4	13
valid_sources[0x23]	322042	1			T3	464		T6	311		T7	302
valid_sources[0x24]	268689	1			T1	1		T3	452		T4	31
valid_sources[0x25]	282224	1			T3	417		T6	300		T7	340
valid_sources[0x26]	258420	1			T1	1		T3	466		T6	291
valid_sources[0x27]	299947	1			T1	1		T3	468		T6	316
valid_sources[0x28]	329209	1			T3	423		T4	65		T6	310
valid_sources[0x29]	279592	1			T1	1		T2	44		T3	462
valid_sources[0x2a]	324255	1			T1	3		T2	66		T3	508
valid_sources[0x2b]	332621	1			T1	2		T3	442		T6	306
valid_sources[0x2c]	274909	1			T1	3		T3	438		T6	309
valid_sources[0x2d]	247378	1			T1	3		T3	463		T6	300
valid_sources[0x2e]	312061	1			T1	3		T3	485		T6	299
valid_sources[0x2f]	262615	1			T1	1		T3	456		T6	330
valid_sources[0x30]	380379	1			T3	440		T6	300		T7	335
valid_sources[0x31]	300864	1			T2	6090		T3	490		T4	176
valid_sources[0x32]	313222	1			T3	459		T6	305		T7	292
valid_sources[0x33]	277698	1			T1	1		T3	429		T6	328
valid_sources[0x34]	259729	1			T1	1		T3	430		T4	96
valid_sources[0x35]	287348	1			T1	1		T3	506		T6	325
valid_sources[0x36]	275452	1			T1	2		T3	487		T4	50
valid_sources[0x37]	262867	1			T2	12968		T3	437		T4	16
valid_sources[0x38]	290541	1			T3	466		T6	326		T7	290
valid_sources[0x39]	284989	1			T3	517		T4	98		T6	321
valid_sources[0x3a]	273610	1			T3	448		T6	316		T7	356
valid_sources[0x3b]	343025	1			T1	1		T3	413		T6	346
valid_sources[0x3c]	279525	1			T1	4		T3	457		T4	5
valid_sources[0x3d]	364499	1			T2	25054		T3	470		T4	27
valid_sources[0x3e]	273847	1			T1	4		T2	26853		T3	473
valid_sources[0x3f]	321089	1			T3	463		T4	9		T6	294
valid_sources[0x40]	244970	1			T1	1		T3	476		T4	49
valid_sources[0x41]	265419	1			T1	3		T3	492		T6	349
valid_sources[0x42]	255815	1			T1	1		T3	430		T6	339
valid_sources[0x43]	291384	1			T1	1		T3	451		T4	54
valid_sources[0x44]	342389	1			T3	455		T6	290		T7	335
valid_sources[0x45]	319645	1			T1	1		T3	473		T6	295
valid_sources[0x46]	319580	1			T1	3		T3	458		T6	331
valid_sources[0x47]	283970	1			T1	2		T3	437		T4	8
valid_sources[0x48]	295843	1			T3	498		T6	303		T7	357
valid_sources[0x49]	288578	1			T1	1		T2	3660		T3	483
valid_sources[0x4a]	249443	1			T1	2		T3	457		T6	303
valid_sources[0x4b]	291772	1			T1	1		T3	504		T6	318
valid_sources[0x4c]	297580	1			T3	472		T6	309		T7	340
valid_sources[0x4d]	257690	1			T1	1		T3	456		T6	357
valid_sources[0x4e]	285793	1			T3	447		T6	279		T7	335
valid_sources[0x4f]	344685	1			T3	445		T6	326		T7	273
valid_sources[0x50]	236657	1			T1	2		T3	459		T6	308
valid_sources[0x51]	265986	1			T1	3		T3	416		T6	303
valid_sources[0x52]	288537	1			T1	1		T3	444		T4	28
valid_sources[0x53]	280238	1			T2	17856		T3	507		T6	349
valid_sources[0x54]	278832	1			T1	2		T3	473		T6	321
valid_sources[0x55]	243604	1			T1	3		T3	441		T6	305
valid_sources[0x56]	268552	1			T3	460		T6	336		T7	437
valid_sources[0x57]	263144	1			T1	3		T3	465		T4	32
valid_sources[0x58]	256434	1			T1	1		T3	463		T6	308
valid_sources[0x59]	328102	1			T1	1		T2	15439		T3	436
valid_sources[0x5a]	310433	1			T1	3		T3	432		T4	129
valid_sources[0x5b]	256066	1			T1	1		T3	516		T6	346
valid_sources[0x5c]	301730	1			T1	1		T3	435		T6	327
valid_sources[0x5d]	266878	1			T1	1		T3	477		T6	315
valid_sources[0x5e]	249060	1			T1	2		T3	447		T4	64
valid_sources[0x5f]	327708	1			T1	1		T3	474		T6	296
valid_sources[0x60]	275376	1			T3	489		T6	321		T7	332
valid_sources[0x61]	411412	1			T1	1		T3	444		T6	313
valid_sources[0x62]	322037	1			T1	1		T3	480		T4	26
valid_sources[0x63]	257309	1			T1	3		T3	521		T4	34
valid_sources[0x64]	273792	1			T1	4		T3	460		T6	312
valid_sources[0x65]	279821	1			T1	5		T3	423		T6	315
valid_sources[0x66]	262757	1			T1	1		T3	490		T6	331
valid_sources[0x67]	242246	1			T3	449		T6	295		T7	358
valid_sources[0x68]	255786	1			T3	483		T6	320		T7	314
valid_sources[0x69]	319026	1			T1	1		T3	497		T6	328
valid_sources[0x6a]	353304	1			T2	2639		T3	413		T6	290
valid_sources[0x6b]	274125	1			T3	461		T6	290		T7	278
valid_sources[0x6c]	274647	1			T3	431		T6	322		T7	313
valid_sources[0x6d]	260565	1			T1	1		T3	522		T6	316
valid_sources[0x6e]	280905	1			T1	1		T3	455		T6	313
valid_sources[0x6f]	280340	1			T1	2		T2	3031		T3	453
valid_sources[0x70]	254090	1			T1	1		T3	496		T6	300
valid_sources[0x71]	242564	1			T1	1		T3	493		T6	323
valid_sources[0x72]	261988	1			T1	2		T3	475		T6	324
valid_sources[0x73]	291576	1			T1	5		T3	457		T6	313
valid_sources[0x74]	325161	1			T1	1		T3	488		T6	317
valid_sources[0x75]	334150	1			T3	495		T6	296		T7	350
valid_sources[0x76]	276708	1			T3	503		T6	346		T7	398
valid_sources[0x77]	303320	1			T1	1		T3	445		T6	327
valid_sources[0x78]	258306	1			T1	1		T2	4638		T3	430
valid_sources[0x79]	245447	1			T1	1		T3	487		T4	33
valid_sources[0x7a]	291080	1			T3	437		T6	315		T7	317
valid_sources[0x7b]	280350	1			T1	1		T3	484		T6	317
valid_sources[0x7c]	318742	1			T3	452		T4	73		T6	312
valid_sources[0x7d]	265244	1			T3	492		T6	312		T7	355
valid_sources[0x7e]	253456	1			T1	2		T3	489		T6	299
valid_sources[0x7f]	266185	1			T1	2		T3	443		T6	293
valid_sources[0x80]	324612	1			T1	3		T3	468		T6	292

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29487408

1

T1

138

T2

98766

T3

53484

values[0x0]

all_enables

biggest_size

14841684

1

T1

93

T2

49178

T3

27241

values[0x1]

all_enables

biggest_size

14843043

1

T1

63

T2

49143

T3

26836

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140243

1

T1

2

T2

28

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51381	1			T1	3		T2	19		T4	37
values[0x0]	59943	1			T1	3		T2	39		T3	8
values[0x1]	63774	1			T1	1		T2	43		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148398

1

T1

2

T2

37

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	634	1			T62	1		T146	1		T28	12
valid_sources[0x01]	727	1			T155	1		T147	3		T86	1
valid_sources[0x02]	712	1			T147	2		T156	8		T26	4
valid_sources[0x03]	582	1			T62	3		T23	1		T144	1
valid_sources[0x04]	679	1			T23	1		T144	1		T53	1
valid_sources[0x05]	589	1			T22	3		T27	1		T28	5
valid_sources[0x06]	522	1			T62	2		T143	1		T144	2
valid_sources[0x07]	496	1			T157	1		T23	3		T56	1
valid_sources[0x08]	838	1			T62	1		T85	1		T158	1
valid_sources[0x09]	797	1			T62	1		T159	2		T160	1
valid_sources[0x0a]	709	1			T63	1		T141	1		T158	1
valid_sources[0x0b]	1207	1			T6	1		T101	1		T54	1
valid_sources[0x0c]	471	1			T141	1		T143	1		T148	1
valid_sources[0x0d]	835	1			T2	4		T98	1		T102	3
valid_sources[0x0e]	612	1			T6	1		T62	1		T27	1
valid_sources[0x0f]	535	1			T6	1		T143	1		T53	1
valid_sources[0x10]	616	1			T62	2		T55	2		T28	10
valid_sources[0x11]	603	1			T2	3		T62	1		T63	1
valid_sources[0x12]	590	1			T12	1		T62	1		T63	1
valid_sources[0x13]	649	1			T2	5		T63	1		T145	1
valid_sources[0x14]	527	1			T161	1		T23	1		T147	5
valid_sources[0x15]	692	1			T6	1		T62	2		T23	1
valid_sources[0x16]	655	1			T84	3		T23	1		T162	1
valid_sources[0x17]	731	1			T163	2		T143	1		T56	2
valid_sources[0x18]	754	1			T1	2		T63	1		T144	2
valid_sources[0x19]	717	1			T144	1		T164	1		T26	6
valid_sources[0x1a]	659	1			T145	2		T28	6		T46	19
valid_sources[0x1b]	611	1			T78	1		T62	1		T99	1
valid_sources[0x1c]	541	1			T62	2		T23	4		T144	1
valid_sources[0x1d]	715	1			T7	2		T63	1		T158	2
valid_sources[0x1e]	739	1			T12	1		T62	1		T161	1
valid_sources[0x1f]	598	1			T99	1		T147	1		T27	2
valid_sources[0x20]	585	1			T63	1		T145	3		T147	3
valid_sources[0x21]	573	1			T144	2		T147	4		T146	2
valid_sources[0x22]	511	1			T2	3		T62	1		T165	1
valid_sources[0x23]	751	1			T62	2		T28	9		T46	8
valid_sources[0x24]	670	1			T1	4		T62	1		T63	1
valid_sources[0x25]	841	1			T146	2		T156	3		T28	9
valid_sources[0x26]	657	1			T146	1		T28	12		T46	19
valid_sources[0x27]	605	1			T63	1		T166	1		T143	1
valid_sources[0x28]	603	1			T10	16		T62	1		T23	2
valid_sources[0x29]	764	1			T23	1		T158	1		T167	17
valid_sources[0x2a]	736	1			T6	1		T78	4		T62	1
valid_sources[0x2b]	848	1			T168	1		T62	2		T143	1
valid_sources[0x2c]	766	1			T23	1		T27	139		T28	11
valid_sources[0x2d]	919	1			T78	2		T144	1		T156	6
valid_sources[0x2e]	598	1			T62	1		T102	1		T23	2
valid_sources[0x2f]	645	1			T62	1		T169	1		T27	124
valid_sources[0x30]	708	1			T2	3		T62	2		T23	1
valid_sources[0x31]	674	1			T2	2		T3	2		T22	3
valid_sources[0x32]	756	1			T141	1		T23	1		T144	3
valid_sources[0x33]	623	1			T8	2		T170	5		T56	1
valid_sources[0x34]	755	1			T12	1		T20	82		T141	2
valid_sources[0x35]	544	1			T157	1		T23	1		T171	71
valid_sources[0x36]	754	1			T6	1		T84	1		T144	1
valid_sources[0x37]	545	1			T62	1		T22	19		T84	3
valid_sources[0x38]	858	1			T159	2		T147	3		T56	1
valid_sources[0x39]	504	1			T6	1		T7	4		T56	1
valid_sources[0x3a]	702	1			T99	1		T143	1		T144	1
valid_sources[0x3b]	807	1			T23	1		T144	1		T158	2
valid_sources[0x3c]	572	1			T62	1		T145	1		T31	1
valid_sources[0x3d]	790	1			T2	2		T7	1		T168	2
valid_sources[0x3e]	775	1			T11	1		T62	2		T158	2
valid_sources[0x3f]	623	1			T143	1		T159	1		T28	10
valid_sources[0x40]	561	1			T143	4		T144	1		T145	1
valid_sources[0x41]	664	1			T44	4		T62	2		T147	4
valid_sources[0x42]	659	1			T23	1		T156	1		T172	1
valid_sources[0x43]	892	1			T169	1		T28	14		T46	12
valid_sources[0x44]	558	1			T62	2		T155	4		T144	1
valid_sources[0x45]	569	1			T12	1		T62	2		T23	1
valid_sources[0x46]	675	1			T2	2		T141	2		T145	2
valid_sources[0x47]	774	1			T2	1		T62	3		T23	1
valid_sources[0x48]	836	1			T6	1		T12	1		T62	1
valid_sources[0x49]	636	1			T62	3		T63	1		T147	1
valid_sources[0x4a]	528	1			T78	3		T62	1		T84	5
valid_sources[0x4b]	1015	1			T2	9		T85	1		T144	1
valid_sources[0x4c]	656	1			T62	1		T173	1		T87	10
valid_sources[0x4d]	689	1			T145	1		T165	1		T156	6
valid_sources[0x4e]	713	1			T62	3		T23	1		T128	4
valid_sources[0x4f]	520	1			T1	1		T63	1		T158	1
valid_sources[0x50]	691	1			T146	2		T169	1		T28	8
valid_sources[0x51]	544	1			T6	1		T144	2		T156	2
valid_sources[0x52]	717	1			T75	1		T170	3		T84	3
valid_sources[0x53]	495	1			T2	1		T62	4		T158	4
valid_sources[0x54]	559	1			T62	1		T63	3		T84	3
valid_sources[0x55]	747	1			T2	2		T143	3		T54	1
valid_sources[0x56]	534	1			T78	1		T141	1		T144	1
valid_sources[0x57]	707	1			T2	6		T141	1		T23	1
valid_sources[0x58]	581	1			T75	1		T166	1		T144	3
valid_sources[0x59]	584	1			T23	1		T143	1		T145	1
valid_sources[0x5a]	867	1			T3	5		T5	12		T62	1
valid_sources[0x5b]	716	1			T6	1		T141	1		T143	1
valid_sources[0x5c]	771	1			T12	1		T143	1		T159	3
valid_sources[0x5d]	553	1			T62	1		T143	1		T145	1
valid_sources[0x5e]	890	1			T62	1		T85	1		T145	1
valid_sources[0x5f]	640	1			T6	1		T62	1		T21	13
valid_sources[0x60]	856	1			T62	1		T23	2		T147	5
valid_sources[0x61]	938	1			T105	2		T174	2		T158	1
valid_sources[0x62]	636	1			T18	2		T23	1		T145	1
valid_sources[0x63]	586	1			T62	1		T22	1		T141	1
valid_sources[0x64]	720	1			T78	1		T23	2		T86	2
valid_sources[0x65]	466	1			T29	1		T156	4		T175	2
valid_sources[0x66]	920	1			T63	3		T144	1		T146	2
valid_sources[0x67]	653	1			T62	2		T144	1		T145	1
valid_sources[0x68]	576	1			T62	1		T63	1		T23	1
valid_sources[0x69]	562	1			T62	2		T85	2		T53	1
valid_sources[0x6a]	766	1			T78	2		T85	2		T147	1
valid_sources[0x6b]	509	1			T144	2		T28	6		T46	13
valid_sources[0x6c]	593	1			T5	18		T151	3		T141	2
valid_sources[0x6d]	675	1			T2	1		T143	1		T152	1
valid_sources[0x6e]	578	1			T63	1		T141	1		T85	3
valid_sources[0x6f]	733	1			T2	1		T62	3		T63	1
valid_sources[0x70]	681	1			T62	3		T45	32		T141	1
valid_sources[0x71]	1008	1			T62	1		T142	137		T172	1
valid_sources[0x72]	463	1			T74	1		T30	1		T146	1
valid_sources[0x73]	981	1			T3	6		T168	1		T85	2
valid_sources[0x74]	767	1			T62	1		T86	4		T176	2
valid_sources[0x75]	768	1			T62	1		T23	1		T145	2
valid_sources[0x76]	606	1			T161	1		T144	1		T145	5
valid_sources[0x77]	630	1			T10	6		T62	2		T143	2
valid_sources[0x78]	750	1			T144	1		T28	4		T46	11
valid_sources[0x79]	700	1			T62	1		T148	9		T172	1
valid_sources[0x7a]	903	1			T168	1		T23	1		T147	4
valid_sources[0x7b]	613	1			T2	1		T7	2		T145	2
valid_sources[0x7c]	704	1			T23	1		T28	7		T46	13
valid_sources[0x7d]	588	1			T2	5		T166	1		T141	1
valid_sources[0x7e]	551	1			T156	4		T160	1		T177	2
valid_sources[0x7f]	786	1			T62	4		T75	3		T178	3
valid_sources[0x80]	713	1			T2	3		T7	2		T62	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38691

1

T1

1

T2

11

T4

17

values[0x0]

all_enables

biggest_size

51713

1

T1

1

T2

11

T3

5

values[0x1]

all_enables

biggest_size

49839

1

T2

6

T3

1

T4

2