Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14118595

1

T1

3

T2

15762

T3

8671

full_word

54221900

1

T1

27

T2

157556

T3

86103

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68340185	1			T1	30		T2	173318		T3	94774
auto[TlIntgErrCmd]	131	1			T106	9		T107	11		T108	4
auto[TlIntgErrData]	79	1			T106	6		T107	3		T108	3
auto[TlIntgErrBoth]	100	1			T106	5		T107	6		T108	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31369805

1

T1

11

T2

65038

T3

35259

auto[1]

36970690

1

T1

19

T2

108280

T3

59515

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6759482	1			T1	1		T2	5803		T3	3233
auto[TlIntgErrNone]	partial	auto[1]	7358829	1			T1	2		T2	9959		T3	5438
auto[TlIntgErrNone]	full_word	auto[0]	24610194	1			T1	10		T2	59235		T3	32026
auto[TlIntgErrNone]	full_word	auto[1]	29611680	1			T1	17		T2	98321		T3	54077
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T106	2		T107	6		T108	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T106	5		T107	4		T108	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T106	2		T108	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T107	1		T137	2		-	-
auto[TlIntgErrData]	partial	auto[0]	24	1			T106	1		T107	1		T108	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T106	5		T107	2		T108	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T129	2		T135	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T131	1		T138	1		T134	3
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T106	3		T107	1		T108	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T106	2		T107	5		T108	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T139	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T133	1		T132	1		T140	1