Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	667370	1			T3	834		T6	457		T7	313
auto[1]	11272204	1			T2	5838		T3	192		T4	5
auto[2]	560635	1			T3	727		T4	1		T6	299
auto[3]	11169093	1			T1	1		T2	5744		T3	112

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14620933	1			T1	1		T2	9596		T3	1445
auto[1]	2348473	1			T2	958		T3	204		T4	1
auto[2]	2341568	1			T2	919		T3	185		T6	141
auto[3]	4358328	1			T2	109		T3	31		T6	15

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8019686

1

T1

1

T2

11571

T3

1862

auto[1]

15649616

1

T2

11

T3

3

T11

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	295656	1			T3	674		T6	381		T7	258
auto[0]	auto[0]	auto[1]	29930	1			T3	74		T6	33		T7	22
auto[0]	auto[0]	auto[2]	30015	1			T3	78		T6	41		T7	32
auto[0]	auto[0]	auto[3]	7188	1			T3	5		T6	2		T7	1
auto[0]	auto[1]	auto[0]	3000843	1			T2	4797		T3	97		T4	5
auto[0]	auto[1]	auto[1]	321216	1			T2	489		T3	78		T6	33
auto[0]	auto[1]	auto[2]	302841	1			T2	476		T3	7		T6	26
auto[0]	auto[1]	auto[3]	70375	1			T2	68		T3	10		T6	4
auto[0]	auto[2]	auto[0]	254412	1			T3	620		T4	1		T6	234
auto[0]	auto[2]	auto[1]	26166	1			T3	50		T6	31		T7	18
auto[0]	auto[2]	auto[2]	24264	1			T3	48		T6	30		T7	19
auto[0]	auto[2]	auto[3]	5491	1			T3	9		T6	4		T77	2
auto[0]	auto[3]	auto[0]	2962131	1			T1	1		T2	4790		T3	51
auto[0]	auto[3]	auto[1]	298449	1			T2	467		T3	2		T4	1
auto[0]	auto[3]	auto[2]	316886	1			T2	443		T3	52		T6	44
auto[0]	auto[3]	auto[3]	73823	1			T2	41		T3	7		T6	5
auto[1]	auto[0]	auto[0]	10393	1			T3	3		T62	12		T97	901
auto[1]	auto[0]	auto[1]	45251	1			T62	2		T97	4232		T151	1
auto[1]	auto[0]	auto[2]	45584	1			T62	4		T97	4335		T152	1
auto[1]	auto[0]	auto[3]	203353	1			T97	19428		T149	16110		T150	2
auto[1]	auto[1]	auto[0]	4046797	1			T2	6		T12	107660		T43	40
auto[1]	auto[1]	auto[1]	802029	1			T2	2		T12	11011		T43	3
auto[1]	auto[1]	auto[2]	792991	1			T12	10788		T43	5		T44	2
auto[1]	auto[1]	auto[3]	1935112	1			T12	1130		T43	1		T25	6545
auto[1]	auto[2]	auto[0]	9045	1			T62	21		T97	919		T151	7
auto[1]	auto[2]	auto[1]	39739	1			T97	3966		T151	1		T152	1
auto[1]	auto[2]	auto[2]	36492	1			T62	1		T97	3606		T151	1
auto[1]	auto[2]	auto[3]	165026	1			T97	16352		T153	1		T149	11003
auto[1]	auto[3]	auto[0]	4041656	1			T2	3		T12	108166		T43	44
auto[1]	auto[3]	auto[1]	785693	1			T12	10947		T43	1		T44	1
auto[1]	auto[3]	auto[2]	792495	1			T12	10977		T43	6		T25	1465
auto[1]	auto[3]	auto[3]	1897960	1			T11	1		T12	1071		T25	6579