Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	300984766	126891	0	0
ctrl_regwen_rd_A	300984766	7470	0	0
exec_rd_A	300984766	7267	0	0
exec_regwen_rd_A	300984766	7989	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300984766	126891	0	0
T26	46486	1411	0	0
T27	0	1587	0	0
T28	0	1907	0	0
T46	0	2470	0	0
T47	0	1039	0	0
T48	0	4314	0	0
T49	0	1114	0	0
T50	0	2002	0	0
T51	0	4194	0	0
T52	0	4697	0	0
T53	343173	0	0	0
T54	152955	0	0	0
T55	943562	0	0	0
T56	451850	0	0	0
T57	99985	0	0	0
T58	57838	0	0	0
T59	56178	0	0	0
T60	383814	0	0	0
T61	119702	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300984766	7470	0	0
T27	69793	368	0	0
T28	0	196	0	0
T110	0	240	0	0
T111	0	203	0	0
T112	0	312	0	0
T113	0	384	0	0
T114	0	627	0	0
T115	0	278	0	0
T116	0	1314	0	0
T117	0	544	0	0
T118	37895	0	0	0
T119	33189	0	0	0
T120	6499	0	0	0
T121	2122	0	0	0
T122	12354	0	0	0
T123	14629	0	0	0
T124	4383	0	0	0
T125	166024	0	0	0
T126	33595	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300984766	7267	0	0
T27	69793	265	0	0
T28	0	177	0	0
T110	0	102	0	0
T111	0	237	0	0
T112	0	405	0	0
T113	0	459	0	0
T114	0	576	0	0
T115	0	288	0	0
T116	0	1128	0	0
T117	0	417	0	0
T118	37895	0	0	0
T119	33189	0	0	0
T120	6499	0	0	0
T121	2122	0	0	0
T122	12354	0	0	0
T123	14629	0	0	0
T124	4383	0	0	0
T125	166024	0	0	0
T126	33595	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300984766	7989	0	0
T27	69793	325	0	0
T28	0	249	0	0
T110	0	211	0	0
T111	0	288	0	0
T112	0	460	0	0
T113	0	477	0	0
T114	0	533	0	0
T115	0	219	0	0
T116	0	1294	0	0
T117	0	609	0	0
T118	37895	0	0	0
T119	33189	0	0	0
T120	6499	0	0	0
T121	2122	0	0	0
T122	12354	0	0	0
T123	14629	0	0	0
T124	4383	0	0	0
T125	166024	0	0	0
T126	33595	0	0	0