Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	142856102	1			T1	15986		T2	206034		T4	3884
instr_valid_dis	114682907	1			T1	15986		T2	147960		T4	3884
instr_en	19079290	1			T2	58074		T5	193698		T16	12918

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9650686	1			T5	123730		T16	73218		T14	34984
sram_ifetch_valid_disable	110463329	1			T1	15986		T2	85694		T4	3884
sram_ifetch_enable	22742087	1			T2	120340		T5	256378		T16	196560

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	142856102	1			T1	15986		T2	206034		T4	3884
hw_debug_en_valid_off	110607086	1			T1	15986		T2	68882		T4	3884
hw_debug_en_on	22175695	1			T2	37408		T5	259830		T16	61496

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110463329	1			T1	15986		T2	85694		T4	3884
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99523020	1			T1	15986		T2	58944		T4	3884
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7371738	1			T2	26750		T5	44728		T16	12918
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3893388	1			T5	51560		T16	54418		T14	34984
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1912758	1			T5	18626		T16	54418		T14	34984
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1380128	1			T47	68928		T8	3416		T64	5966
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3764124	1			T5	72170		T26	16372		T8	79192
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1553452	1			T5	15162		T26	16372		T8	79192
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1474284	1			T64	20000		T116	21232		T137	13240
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8795979	1			T2	19024		T5	115572		T16	12826
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4205785	1			T2	19024		T5	95198		T26	90336
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3016268	1			T5	20374		T16	12826		T8	18756

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8057934	1			T2	31324		T5	148970		T14	84594
lc_exec_en	9615592	1			T2	18384		T5	72088		T16	48670
valid_exec_dis	108303679	1			T1	15986		T2	113572		T4	3884
invalid_exec_dis	32392773	1			T2	120340		T5	380108		T16	269778