Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42846563	1			T1	7299		T2	37532		T4	93
triple_byte_access	2471701	1			T1	129		T2	732		T4	217
halfword_access	3710112	1			T1	233		T2	1144		T4	428
byte_access	4957957	1			T1	259		T2	1526		T4	803
zero_access	1246925	1			T1	73		T2	355		T4	401

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27558959

1

T1

3966

T2

20657

T4

865

auto[1]

27674299

1

T1

4027

T2

20632

T4

1077

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21368750	1			T1	3600		T2	18790		T4	7
auto[0]	triple_byte_access	1231973	1			T1	64		T2	372		T4	33
auto[0]	halfword_access	1851875	1			T1	128		T2	586		T4	116
auto[0]	byte_access	2478094	1			T1	132		T2	729		T4	401
auto[0]	zero_access	628267	1			T1	42		T2	180		T4	308
auto[1]	word_access	21477813	1			T1	3699		T2	18742		T4	86
auto[1]	triple_byte_access	1239728	1			T1	65		T2	360		T4	184
auto[1]	halfword_access	1858237	1			T1	105		T2	558		T4	312
auto[1]	byte_access	2479863	1			T1	127		T2	797		T4	402
auto[1]	zero_access	618658	1			T1	31		T2	175		T4	93