T34 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1877116723 |
|
|
May 23 12:49:46 PM PDT 24 |
May 23 12:49:51 PM PDT 24 |
648337570 ps |
T789 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2554091503 |
|
|
May 23 12:52:48 PM PDT 24 |
May 23 12:56:18 PM PDT 24 |
9062028041 ps |
T790 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1785584741 |
|
|
May 23 12:51:32 PM PDT 24 |
May 23 12:55:31 PM PDT 24 |
2705509452 ps |
T791 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.943642162 |
|
|
May 23 12:50:14 PM PDT 24 |
May 23 12:50:20 PM PDT 24 |
75692219 ps |
T792 |
/workspace/coverage/default/27.sram_ctrl_alert_test.4261651550 |
|
|
May 23 12:51:23 PM PDT 24 |
May 23 12:51:25 PM PDT 24 |
14763268 ps |
T793 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1365849909 |
|
|
May 23 12:53:03 PM PDT 24 |
May 23 12:53:09 PM PDT 24 |
279267506 ps |
T794 |
/workspace/coverage/default/16.sram_ctrl_regwen.3792398840 |
|
|
May 23 12:50:30 PM PDT 24 |
May 23 01:02:32 PM PDT 24 |
5630925875 ps |
T795 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1132087909 |
|
|
May 23 12:52:28 PM PDT 24 |
May 23 12:52:30 PM PDT 24 |
16684371 ps |
T796 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1351667171 |
|
|
May 23 12:50:09 PM PDT 24 |
May 23 12:50:59 PM PDT 24 |
1962361514 ps |
T797 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.805562399 |
|
|
May 23 12:51:54 PM PDT 24 |
May 23 12:57:07 PM PDT 24 |
13010655992 ps |
T798 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2707023955 |
|
|
May 23 12:50:27 PM PDT 24 |
May 23 12:59:54 PM PDT 24 |
25483364315 ps |
T799 |
/workspace/coverage/default/16.sram_ctrl_executable.3320314851 |
|
|
May 23 12:50:28 PM PDT 24 |
May 23 01:04:56 PM PDT 24 |
3032026418 ps |
T800 |
/workspace/coverage/default/38.sram_ctrl_bijection.3907249801 |
|
|
May 23 12:52:24 PM PDT 24 |
May 23 12:53:10 PM PDT 24 |
5742817480 ps |
T801 |
/workspace/coverage/default/3.sram_ctrl_regwen.2095488427 |
|
|
May 23 12:49:35 PM PDT 24 |
May 23 01:04:17 PM PDT 24 |
54289164251 ps |
T802 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2445004501 |
|
|
May 23 12:49:36 PM PDT 24 |
May 23 12:51:40 PM PDT 24 |
596637953 ps |
T803 |
/workspace/coverage/default/24.sram_ctrl_smoke.441123375 |
|
|
May 23 12:50:53 PM PDT 24 |
May 23 12:51:05 PM PDT 24 |
534796571 ps |
T804 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3131743355 |
|
|
May 23 12:49:32 PM PDT 24 |
May 23 12:50:11 PM PDT 24 |
1803029711 ps |
T805 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2124491172 |
|
|
May 23 12:51:22 PM PDT 24 |
May 23 12:51:39 PM PDT 24 |
1863916126 ps |
T806 |
/workspace/coverage/default/35.sram_ctrl_regwen.3487554191 |
|
|
May 23 12:51:54 PM PDT 24 |
May 23 12:53:16 PM PDT 24 |
1336276710 ps |
T807 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3862216018 |
|
|
May 23 12:51:54 PM PDT 24 |
May 23 12:55:34 PM PDT 24 |
36115520420 ps |
T808 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1971220246 |
|
|
May 23 12:53:17 PM PDT 24 |
May 23 12:53:20 PM PDT 24 |
23474487 ps |
T809 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2258586569 |
|
|
May 23 12:50:01 PM PDT 24 |
May 23 12:50:05 PM PDT 24 |
765699709 ps |
T810 |
/workspace/coverage/default/46.sram_ctrl_executable.2830263749 |
|
|
May 23 12:53:09 PM PDT 24 |
May 23 01:03:11 PM PDT 24 |
24828160251 ps |
T811 |
/workspace/coverage/default/14.sram_ctrl_partial_access.803630132 |
|
|
May 23 12:50:26 PM PDT 24 |
May 23 12:50:47 PM PDT 24 |
15590887325 ps |
T812 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1450267372 |
|
|
May 23 12:49:31 PM PDT 24 |
May 23 12:57:13 PM PDT 24 |
19329555110 ps |
T813 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2233955795 |
|
|
May 23 12:53:04 PM PDT 24 |
May 23 12:53:10 PM PDT 24 |
1167070511 ps |
T814 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3134370111 |
|
|
May 23 12:50:07 PM PDT 24 |
May 23 12:52:31 PM PDT 24 |
7309126888 ps |
T815 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.2195483269 |
|
|
May 23 12:49:46 PM PDT 24 |
May 23 12:49:49 PM PDT 24 |
41866958 ps |
T816 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.748947654 |
|
|
May 23 12:50:32 PM PDT 24 |
May 23 12:50:36 PM PDT 24 |
95464155 ps |
T817 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3718963404 |
|
|
May 23 12:50:49 PM PDT 24 |
May 23 12:51:36 PM PDT 24 |
597691989 ps |
T818 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1332885678 |
|
|
May 23 12:52:23 PM PDT 24 |
May 23 12:56:24 PM PDT 24 |
9417866932 ps |
T819 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3466876643 |
|
|
May 23 12:51:58 PM PDT 24 |
May 23 12:52:05 PM PDT 24 |
613466489 ps |
T820 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1593543448 |
|
|
May 23 12:50:15 PM PDT 24 |
May 23 12:51:35 PM PDT 24 |
14372030381 ps |
T821 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2946554960 |
|
|
May 23 12:51:46 PM PDT 24 |
May 23 12:56:24 PM PDT 24 |
6255198604 ps |
T822 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.871755581 |
|
|
May 23 12:50:03 PM PDT 24 |
May 23 01:03:53 PM PDT 24 |
11795691719 ps |
T823 |
/workspace/coverage/default/18.sram_ctrl_regwen.867145960 |
|
|
May 23 12:50:27 PM PDT 24 |
May 23 12:59:54 PM PDT 24 |
34380285403 ps |
T824 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3960788864 |
|
|
May 23 12:51:08 PM PDT 24 |
May 23 12:54:32 PM PDT 24 |
12255994652 ps |
T825 |
/workspace/coverage/default/29.sram_ctrl_alert_test.451342624 |
|
|
May 23 12:51:32 PM PDT 24 |
May 23 12:51:36 PM PDT 24 |
129160237 ps |
T826 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2336855413 |
|
|
May 23 12:52:27 PM PDT 24 |
May 23 12:56:40 PM PDT 24 |
10190938814 ps |
T827 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3995814039 |
|
|
May 23 12:50:02 PM PDT 24 |
May 23 12:52:32 PM PDT 24 |
2120892860 ps |
T828 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.698490261 |
|
|
May 23 12:51:55 PM PDT 24 |
May 23 12:52:05 PM PDT 24 |
183922254 ps |
T829 |
/workspace/coverage/default/1.sram_ctrl_regwen.3901985734 |
|
|
May 23 12:49:34 PM PDT 24 |
May 23 01:09:46 PM PDT 24 |
15099232227 ps |
T830 |
/workspace/coverage/default/23.sram_ctrl_smoke.3940840589 |
|
|
May 23 12:50:52 PM PDT 24 |
May 23 12:51:37 PM PDT 24 |
339981747 ps |
T831 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1753915226 |
|
|
May 23 12:52:08 PM PDT 24 |
May 23 12:52:13 PM PDT 24 |
65454239 ps |
T832 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.809380929 |
|
|
May 23 12:50:30 PM PDT 24 |
May 23 01:04:21 PM PDT 24 |
14969669862 ps |
T833 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1518014465 |
|
|
May 23 12:53:34 PM PDT 24 |
May 23 12:53:46 PM PDT 24 |
524283232 ps |
T834 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3939697345 |
|
|
May 23 12:51:43 PM PDT 24 |
May 23 12:57:44 PM PDT 24 |
54821177003 ps |
T835 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2327037527 |
|
|
May 23 12:49:32 PM PDT 24 |
May 23 12:49:39 PM PDT 24 |
475854288 ps |
T836 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2017298565 |
|
|
May 23 12:50:52 PM PDT 24 |
May 23 12:51:00 PM PDT 24 |
951652428 ps |
T837 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3918236037 |
|
|
May 23 12:51:35 PM PDT 24 |
May 23 12:51:40 PM PDT 24 |
134073858 ps |
T838 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.884306676 |
|
|
May 23 12:50:02 PM PDT 24 |
May 23 01:09:42 PM PDT 24 |
8368686475 ps |
T839 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3284218949 |
|
|
May 23 12:51:22 PM PDT 24 |
May 23 12:51:25 PM PDT 24 |
28744165 ps |
T840 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3708782452 |
|
|
May 23 12:51:34 PM PDT 24 |
May 23 12:51:43 PM PDT 24 |
212875340 ps |
T841 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2075470317 |
|
|
May 23 12:50:14 PM PDT 24 |
May 23 12:52:12 PM PDT 24 |
6322572239 ps |
T842 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3161718361 |
|
|
May 23 12:50:30 PM PDT 24 |
May 23 12:58:23 PM PDT 24 |
1114751089 ps |
T843 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.219224908 |
|
|
May 23 12:50:40 PM PDT 24 |
May 23 12:50:50 PM PDT 24 |
1605471031 ps |
T844 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1337215368 |
|
|
May 23 12:52:49 PM PDT 24 |
May 23 12:58:53 PM PDT 24 |
1102314280 ps |
T845 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1000987267 |
|
|
May 23 12:52:35 PM PDT 24 |
May 23 12:52:46 PM PDT 24 |
456575890 ps |
T846 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2801942641 |
|
|
May 23 12:50:30 PM PDT 24 |
May 23 12:56:49 PM PDT 24 |
58170160151 ps |
T847 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1293938230 |
|
|
May 23 12:51:31 PM PDT 24 |
May 23 12:56:55 PM PDT 24 |
19334473343 ps |
T848 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1762672798 |
|
|
May 23 12:51:34 PM PDT 24 |
May 23 12:53:16 PM PDT 24 |
227671200 ps |
T849 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2084944331 |
|
|
May 23 12:51:20 PM PDT 24 |
May 23 12:51:27 PM PDT 24 |
208075870 ps |
T850 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1603571091 |
|
|
May 23 12:50:02 PM PDT 24 |
May 23 12:55:12 PM PDT 24 |
13231600913 ps |
T851 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3047421564 |
|
|
May 23 12:51:34 PM PDT 24 |
May 23 12:51:40 PM PDT 24 |
46402144 ps |
T852 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.79752227 |
|
|
May 23 12:50:50 PM PDT 24 |
May 23 12:56:02 PM PDT 24 |
13593998602 ps |
T853 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3193765262 |
|
|
May 23 12:50:25 PM PDT 24 |
May 23 12:50:47 PM PDT 24 |
660656999 ps |
T854 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1875237668 |
|
|
May 23 12:49:43 PM PDT 24 |
May 23 12:51:52 PM PDT 24 |
557039363 ps |
T855 |
/workspace/coverage/default/5.sram_ctrl_regwen.1076802260 |
|
|
May 23 12:49:40 PM PDT 24 |
May 23 12:52:10 PM PDT 24 |
7500610568 ps |
T856 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.4142379309 |
|
|
May 23 12:49:36 PM PDT 24 |
May 23 12:49:39 PM PDT 24 |
39118937 ps |
T857 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.981830541 |
|
|
May 23 12:50:28 PM PDT 24 |
May 23 12:50:41 PM PDT 24 |
69993295 ps |
T858 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3450333277 |
|
|
May 23 12:49:47 PM PDT 24 |
May 23 12:49:50 PM PDT 24 |
36075832 ps |
T859 |
/workspace/coverage/default/43.sram_ctrl_regwen.644288547 |
|
|
May 23 12:52:50 PM PDT 24 |
May 23 01:03:39 PM PDT 24 |
70628954319 ps |
T860 |
/workspace/coverage/default/19.sram_ctrl_regwen.347874740 |
|
|
May 23 12:50:31 PM PDT 24 |
May 23 12:57:37 PM PDT 24 |
1294438410 ps |
T861 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3833995762 |
|
|
May 23 12:49:43 PM PDT 24 |
May 23 12:49:49 PM PDT 24 |
333233032 ps |
T862 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1645139124 |
|
|
May 23 12:52:36 PM PDT 24 |
May 23 12:52:42 PM PDT 24 |
250344300 ps |
T863 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1102054068 |
|
|
May 23 12:49:48 PM PDT 24 |
May 23 12:49:53 PM PDT 24 |
372488704 ps |
T864 |
/workspace/coverage/default/46.sram_ctrl_bijection.162889549 |
|
|
May 23 12:53:07 PM PDT 24 |
May 23 12:53:39 PM PDT 24 |
3109861858 ps |
T865 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1280244203 |
|
|
May 23 12:52:09 PM PDT 24 |
May 23 01:06:01 PM PDT 24 |
4796671602 ps |
T866 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.467395102 |
|
|
May 23 12:50:51 PM PDT 24 |
May 23 12:53:58 PM PDT 24 |
2079978151 ps |
T867 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3973958529 |
|
|
May 23 12:50:02 PM PDT 24 |
May 23 12:51:29 PM PDT 24 |
473513860 ps |
T868 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3359203006 |
|
|
May 23 12:50:15 PM PDT 24 |
May 23 12:50:23 PM PDT 24 |
493393161 ps |
T869 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3670567381 |
|
|
May 23 12:50:50 PM PDT 24 |
May 23 12:50:56 PM PDT 24 |
938444261 ps |
T870 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.89530194 |
|
|
May 23 12:52:08 PM PDT 24 |
May 23 12:52:18 PM PDT 24 |
2737315495 ps |
T871 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.577084896 |
|
|
May 23 12:52:35 PM PDT 24 |
May 23 12:52:44 PM PDT 24 |
4036659361 ps |
T872 |
/workspace/coverage/default/14.sram_ctrl_alert_test.370560129 |
|
|
May 23 12:50:24 PM PDT 24 |
May 23 12:50:26 PM PDT 24 |
12490677 ps |
T873 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2237835844 |
|
|
May 23 12:52:08 PM PDT 24 |
May 23 12:55:31 PM PDT 24 |
1568281737 ps |
T874 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1853667262 |
|
|
May 23 12:50:49 PM PDT 24 |
May 23 12:50:58 PM PDT 24 |
611526900 ps |
T875 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3062784997 |
|
|
May 23 12:49:46 PM PDT 24 |
May 23 12:49:57 PM PDT 24 |
333181606 ps |
T876 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.143542768 |
|
|
May 23 12:53:02 PM PDT 24 |
May 23 01:02:56 PM PDT 24 |
1419548922 ps |
T877 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.4239549834 |
|
|
May 23 12:53:19 PM PDT 24 |
May 23 01:03:33 PM PDT 24 |
14375992030 ps |
T878 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.366920004 |
|
|
May 23 12:50:14 PM PDT 24 |
May 23 12:50:24 PM PDT 24 |
1359716158 ps |
T879 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.266515382 |
|
|
May 23 12:51:35 PM PDT 24 |
May 23 01:13:49 PM PDT 24 |
12248151175 ps |
T880 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2718968208 |
|
|
May 23 12:49:36 PM PDT 24 |
May 23 12:54:30 PM PDT 24 |
12507490322 ps |
T881 |
/workspace/coverage/default/18.sram_ctrl_executable.2012849355 |
|
|
May 23 12:50:26 PM PDT 24 |
May 23 12:54:53 PM PDT 24 |
18291369164 ps |
T882 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2528825831 |
|
|
May 23 12:51:52 PM PDT 24 |
May 23 12:52:23 PM PDT 24 |
381031565 ps |
T883 |
/workspace/coverage/default/4.sram_ctrl_regwen.40105162 |
|
|
May 23 12:49:43 PM PDT 24 |
May 23 01:13:30 PM PDT 24 |
11536144649 ps |
T884 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1689971324 |
|
|
May 23 12:51:34 PM PDT 24 |
May 23 12:58:06 PM PDT 24 |
20865198500 ps |
T885 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2076758226 |
|
|
May 23 12:50:15 PM PDT 24 |
May 23 12:56:43 PM PDT 24 |
16549988939 ps |
T886 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3245892798 |
|
|
May 23 12:50:28 PM PDT 24 |
May 23 01:03:43 PM PDT 24 |
3620567565 ps |
T887 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2661558401 |
|
|
May 23 12:49:35 PM PDT 24 |
May 23 01:27:07 PM PDT 24 |
41515314638 ps |
T888 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.366578237 |
|
|
May 23 12:52:24 PM PDT 24 |
May 23 01:06:21 PM PDT 24 |
14695903128 ps |
T889 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1528183472 |
|
|
May 23 12:52:13 PM PDT 24 |
May 23 12:52:21 PM PDT 24 |
167755957 ps |
T890 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.3183850768 |
|
|
May 23 12:51:54 PM PDT 24 |
May 23 12:52:02 PM PDT 24 |
435741763 ps |
T891 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.4257281145 |
|
|
May 23 12:52:39 PM PDT 24 |
May 23 12:52:46 PM PDT 24 |
68976637 ps |
T892 |
/workspace/coverage/default/15.sram_ctrl_stress_all.4107316306 |
|
|
May 23 12:50:26 PM PDT 24 |
May 23 01:43:16 PM PDT 24 |
260786935336 ps |
T893 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.252142380 |
|
|
May 23 12:52:24 PM PDT 24 |
May 23 12:58:55 PM PDT 24 |
5263178769 ps |
T894 |
/workspace/coverage/default/1.sram_ctrl_bijection.110827333 |
|
|
May 23 12:49:34 PM PDT 24 |
May 23 12:49:51 PM PDT 24 |
804335775 ps |
T895 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1035163187 |
|
|
May 23 12:52:11 PM PDT 24 |
May 23 01:00:49 PM PDT 24 |
8229550571 ps |
T896 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.775914488 |
|
|
May 23 12:52:08 PM PDT 24 |
May 23 12:57:03 PM PDT 24 |
6442891024 ps |
T897 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2970949784 |
|
|
May 23 12:49:37 PM PDT 24 |
May 23 12:49:39 PM PDT 24 |
12896268 ps |
T898 |
/workspace/coverage/default/15.sram_ctrl_executable.1544106832 |
|
|
May 23 12:50:26 PM PDT 24 |
May 23 12:50:49 PM PDT 24 |
5411427037 ps |
T899 |
/workspace/coverage/default/17.sram_ctrl_partial_access.4148679826 |
|
|
May 23 12:50:31 PM PDT 24 |
May 23 12:52:09 PM PDT 24 |
387089811 ps |
T900 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3955106423 |
|
|
May 23 12:53:35 PM PDT 24 |
May 23 12:53:57 PM PDT 24 |
4172994331 ps |
T901 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3453821808 |
|
|
May 23 12:50:44 PM PDT 24 |
May 23 12:52:09 PM PDT 24 |
2287275350 ps |
T902 |
/workspace/coverage/default/15.sram_ctrl_regwen.1824231766 |
|
|
May 23 12:50:26 PM PDT 24 |
May 23 01:13:10 PM PDT 24 |
32257035986 ps |
T903 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3059291296 |
|
|
May 23 12:51:34 PM PDT 24 |
May 23 01:53:11 PM PDT 24 |
25879833450 ps |
T904 |
/workspace/coverage/default/4.sram_ctrl_partial_access.2406163324 |
|
|
May 23 12:49:42 PM PDT 24 |
May 23 12:49:49 PM PDT 24 |
102134194 ps |
T905 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3241434711 |
|
|
May 23 12:50:16 PM PDT 24 |
May 23 12:54:20 PM PDT 24 |
2683173759 ps |
T906 |
/workspace/coverage/default/14.sram_ctrl_bijection.3648218498 |
|
|
May 23 12:50:25 PM PDT 24 |
May 23 12:51:30 PM PDT 24 |
7281906157 ps |
T35 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.343838497 |
|
|
May 23 12:49:40 PM PDT 24 |
May 23 12:49:43 PM PDT 24 |
212238381 ps |
T907 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1569851289 |
|
|
May 23 12:51:55 PM PDT 24 |
May 23 01:04:01 PM PDT 24 |
10558391125 ps |
T908 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3481257343 |
|
|
May 23 12:50:33 PM PDT 24 |
May 23 12:50:43 PM PDT 24 |
134325563 ps |
T909 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.939694811 |
|
|
May 23 12:50:25 PM PDT 24 |
May 23 12:50:57 PM PDT 24 |
604819466 ps |
T910 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1089772447 |
|
|
May 23 12:50:28 PM PDT 24 |
May 23 12:54:34 PM PDT 24 |
10453079523 ps |
T911 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1704181891 |
|
|
May 23 12:50:30 PM PDT 24 |
May 23 12:50:36 PM PDT 24 |
52495576 ps |
T912 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2484777993 |
|
|
May 23 12:50:02 PM PDT 24 |
May 23 01:52:30 PM PDT 24 |
123158955142 ps |
T913 |
/workspace/coverage/default/15.sram_ctrl_partial_access.4159922938 |
|
|
May 23 12:50:25 PM PDT 24 |
May 23 12:50:37 PM PDT 24 |
2623068847 ps |
T914 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3838671502 |
|
|
May 23 12:53:02 PM PDT 24 |
May 23 01:23:58 PM PDT 24 |
127827796520 ps |
T915 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4120743658 |
|
|
May 23 12:53:32 PM PDT 24 |
May 23 12:54:48 PM PDT 24 |
227998878 ps |
T916 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2191523112 |
|
|
May 23 12:49:44 PM PDT 24 |
May 23 12:49:51 PM PDT 24 |
1780258170 ps |
T917 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4283098840 |
|
|
May 23 12:49:44 PM PDT 24 |
May 23 01:01:37 PM PDT 24 |
3278722405 ps |
T918 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1293840403 |
|
|
May 23 12:50:29 PM PDT 24 |
May 23 12:52:15 PM PDT 24 |
1981267203 ps |
T919 |
/workspace/coverage/default/45.sram_ctrl_smoke.1115514766 |
|
|
May 23 12:53:04 PM PDT 24 |
May 23 12:54:44 PM PDT 24 |
2449246496 ps |
T920 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2891502415 |
|
|
May 23 12:51:32 PM PDT 24 |
May 23 12:51:35 PM PDT 24 |
13452523 ps |
T921 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.578385740 |
|
|
May 23 12:51:32 PM PDT 24 |
May 23 12:51:39 PM PDT 24 |
448411232 ps |
T922 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1497088216 |
|
|
May 23 12:51:09 PM PDT 24 |
May 23 12:51:12 PM PDT 24 |
36258504 ps |
T923 |
/workspace/coverage/default/43.sram_ctrl_bijection.1851184357 |
|
|
May 23 12:52:50 PM PDT 24 |
May 23 12:53:15 PM PDT 24 |
1447133837 ps |
T924 |
/workspace/coverage/default/37.sram_ctrl_smoke.3997468083 |
|
|
May 23 12:52:10 PM PDT 24 |
May 23 12:52:26 PM PDT 24 |
1853277728 ps |
T925 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.4096456847 |
|
|
May 23 12:50:03 PM PDT 24 |
May 23 01:00:50 PM PDT 24 |
10975434393 ps |
T926 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1891053802 |
|
|
May 23 12:50:02 PM PDT 24 |
May 23 12:50:17 PM PDT 24 |
1538222151 ps |
T927 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2952263173 |
|
|
May 23 12:52:11 PM PDT 24 |
May 23 12:52:20 PM PDT 24 |
1368528054 ps |
T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1800282942 |
|
|
May 23 12:48:27 PM PDT 24 |
May 23 12:48:32 PM PDT 24 |
1442880058 ps |
T94 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3920108360 |
|
|
May 23 12:48:11 PM PDT 24 |
May 23 12:48:13 PM PDT 24 |
14269987 ps |
T101 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2141297736 |
|
|
May 23 12:48:12 PM PDT 24 |
May 23 12:48:15 PM PDT 24 |
227978164 ps |
T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.309147334 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:27 PM PDT 24 |
24156680 ps |
T70 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.640867322 |
|
|
May 23 12:48:52 PM PDT 24 |
May 23 12:48:54 PM PDT 24 |
52189225 ps |
T71 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3549105961 |
|
|
May 23 12:48:11 PM PDT 24 |
May 23 12:48:12 PM PDT 24 |
47066454 ps |
T928 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2221276609 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
13782518 ps |
T929 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4006573088 |
|
|
May 23 12:48:39 PM PDT 24 |
May 23 12:48:42 PM PDT 24 |
48630842 ps |
T930 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2974762575 |
|
|
May 23 12:48:14 PM PDT 24 |
May 23 12:48:16 PM PDT 24 |
1782450437 ps |
T931 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3092647632 |
|
|
May 23 12:48:47 PM PDT 24 |
May 23 12:48:49 PM PDT 24 |
174902190 ps |
T102 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2229236044 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
86081814 ps |
T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.655918295 |
|
|
May 23 12:48:23 PM PDT 24 |
May 23 12:48:25 PM PDT 24 |
20036485 ps |
T103 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1848881770 |
|
|
May 23 12:48:40 PM PDT 24 |
May 23 12:48:44 PM PDT 24 |
241245962 ps |
T932 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2386663284 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:40 PM PDT 24 |
29469637 ps |
T95 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1922131554 |
|
|
May 23 12:48:51 PM PDT 24 |
May 23 12:48:53 PM PDT 24 |
23461370 ps |
T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3313831749 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:40 PM PDT 24 |
44750128 ps |
T96 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.905717641 |
|
|
May 23 12:48:45 PM PDT 24 |
May 23 12:48:46 PM PDT 24 |
41229524 ps |
T74 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.462373936 |
|
|
May 23 12:48:35 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
787046309 ps |
T122 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1008578846 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:27 PM PDT 24 |
167266359 ps |
T75 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3082756062 |
|
|
May 23 12:48:12 PM PDT 24 |
May 23 12:48:16 PM PDT 24 |
179500915 ps |
T933 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3680114893 |
|
|
May 23 12:48:13 PM PDT 24 |
May 23 12:48:18 PM PDT 24 |
42328809 ps |
T934 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3301087200 |
|
|
May 23 12:48:48 PM PDT 24 |
May 23 12:48:51 PM PDT 24 |
32943440 ps |
T76 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1153709124 |
|
|
May 23 12:48:39 PM PDT 24 |
May 23 12:48:44 PM PDT 24 |
448840166 ps |
T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.519281238 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:40 PM PDT 24 |
38856935 ps |
T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2985824094 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:38 PM PDT 24 |
47707861 ps |
T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3234378123 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
37978689 ps |
T935 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1439410431 |
|
|
May 23 12:48:41 PM PDT 24 |
May 23 12:48:46 PM PDT 24 |
451668018 ps |
T936 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1189615268 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:44 PM PDT 24 |
106691141 ps |
T937 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.846213746 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
36804377 ps |
T938 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.87186529 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
96693607 ps |
T939 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.552080341 |
|
|
May 23 12:48:31 PM PDT 24 |
May 23 12:48:33 PM PDT 24 |
110829671 ps |
T940 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.750927217 |
|
|
May 23 12:48:50 PM PDT 24 |
May 23 12:48:53 PM PDT 24 |
87021684 ps |
T80 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1009169306 |
|
|
May 23 12:48:23 PM PDT 24 |
May 23 12:48:25 PM PDT 24 |
14450155 ps |
T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.55048689 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
137442958 ps |
T125 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2604562418 |
|
|
May 23 12:48:26 PM PDT 24 |
May 23 12:48:30 PM PDT 24 |
1211707038 ps |
T123 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3944469824 |
|
|
May 23 12:48:49 PM PDT 24 |
May 23 12:48:52 PM PDT 24 |
629155021 ps |
T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3167727722 |
|
|
May 23 12:48:26 PM PDT 24 |
May 23 12:48:30 PM PDT 24 |
785703342 ps |
T942 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2260921956 |
|
|
May 23 12:48:52 PM PDT 24 |
May 23 12:48:54 PM PDT 24 |
16897493 ps |
T131 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1108421188 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
205047606 ps |
T82 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1622378503 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
1698611928 ps |
T943 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2856131560 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:38 PM PDT 24 |
14046335 ps |
T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4032557180 |
|
|
May 23 12:48:27 PM PDT 24 |
May 23 12:48:31 PM PDT 24 |
154716010 ps |
T124 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.574361448 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
318547499 ps |
T945 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2429992073 |
|
|
May 23 12:48:51 PM PDT 24 |
May 23 12:48:54 PM PDT 24 |
75511144 ps |
T83 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3321982369 |
|
|
May 23 12:48:39 PM PDT 24 |
May 23 12:48:44 PM PDT 24 |
392682232 ps |
T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.879900983 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
486513822 ps |
T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2354749827 |
|
|
May 23 12:48:51 PM PDT 24 |
May 23 12:48:53 PM PDT 24 |
16679959 ps |
T948 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.948191369 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
89942465 ps |
T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1479547037 |
|
|
May 23 12:48:41 PM PDT 24 |
May 23 12:48:43 PM PDT 24 |
106656750 ps |
T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.963193657 |
|
|
May 23 12:48:16 PM PDT 24 |
May 23 12:48:19 PM PDT 24 |
455276911 ps |
T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2143749185 |
|
|
May 23 12:48:11 PM PDT 24 |
May 23 12:48:13 PM PDT 24 |
33870113 ps |
T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2120976034 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
114504662 ps |
T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1762214482 |
|
|
May 23 12:48:13 PM PDT 24 |
May 23 12:48:15 PM PDT 24 |
19969600 ps |
T128 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.754900594 |
|
|
May 23 12:48:49 PM PDT 24 |
May 23 12:48:55 PM PDT 24 |
3974057583 ps |
T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.707862481 |
|
|
May 23 12:48:35 PM PDT 24 |
May 23 12:48:37 PM PDT 24 |
299888137 ps |
T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3569180555 |
|
|
May 23 12:48:17 PM PDT 24 |
May 23 12:48:20 PM PDT 24 |
3092960717 ps |
T955 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1861938240 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
164977470 ps |
T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1103389673 |
|
|
May 23 12:48:49 PM PDT 24 |
May 23 12:48:51 PM PDT 24 |
222833013 ps |
T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.279193609 |
|
|
May 23 12:48:31 PM PDT 24 |
May 23 12:48:32 PM PDT 24 |
14630659 ps |
T958 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2677692842 |
|
|
May 23 12:48:40 PM PDT 24 |
May 23 12:48:43 PM PDT 24 |
841701215 ps |
T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2634372095 |
|
|
May 23 12:48:14 PM PDT 24 |
May 23 12:48:16 PM PDT 24 |
15877317 ps |
T129 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4093286801 |
|
|
May 23 12:48:50 PM PDT 24 |
May 23 12:48:53 PM PDT 24 |
1383296398 ps |
T960 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2019511131 |
|
|
May 23 12:48:49 PM PDT 24 |
May 23 12:48:51 PM PDT 24 |
226094209 ps |
T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3380169217 |
|
|
May 23 12:48:40 PM PDT 24 |
May 23 12:48:42 PM PDT 24 |
44408609 ps |
T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1159782516 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:27 PM PDT 24 |
13438142 ps |
T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1297341943 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
60417974 ps |
T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.377668763 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:29 PM PDT 24 |
130873538 ps |
T965 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.637754082 |
|
|
May 23 12:48:52 PM PDT 24 |
May 23 12:48:57 PM PDT 24 |
101915379 ps |
T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.332320982 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
113165700 ps |
T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1713223381 |
|
|
May 23 12:48:23 PM PDT 24 |
May 23 12:48:25 PM PDT 24 |
29232822 ps |
T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2696653868 |
|
|
May 23 12:48:12 PM PDT 24 |
May 23 12:48:18 PM PDT 24 |
397709118 ps |
T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1546540461 |
|
|
May 23 12:48:11 PM PDT 24 |
May 23 12:48:12 PM PDT 24 |
51415570 ps |
T970 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4002288077 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
22851361 ps |
T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1704951033 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
126959936 ps |
T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3991369350 |
|
|
May 23 12:48:12 PM PDT 24 |
May 23 12:48:14 PM PDT 24 |
23588854 ps |
T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2156514595 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:41 PM PDT 24 |
54904893 ps |
T93 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3713677388 |
|
|
May 23 12:48:50 PM PDT 24 |
May 23 12:48:55 PM PDT 24 |
1913249073 ps |
T974 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.897578815 |
|
|
May 23 12:48:54 PM PDT 24 |
May 23 12:48:57 PM PDT 24 |
447134560 ps |
T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2670498611 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
34473672 ps |
T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4285827727 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:42 PM PDT 24 |
140073398 ps |
T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.920067752 |
|
|
May 23 12:48:12 PM PDT 24 |
May 23 12:48:14 PM PDT 24 |
38156353 ps |
T978 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1958004775 |
|
|
May 23 12:48:39 PM PDT 24 |
May 23 12:48:42 PM PDT 24 |
40136144 ps |
T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1982488899 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
454326401 ps |
T980 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2855101185 |
|
|
May 23 12:48:53 PM PDT 24 |
May 23 12:48:58 PM PDT 24 |
4803353940 ps |
T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1159150487 |
|
|
May 23 12:48:50 PM PDT 24 |
May 23 12:48:52 PM PDT 24 |
49976072 ps |
T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.121498578 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
44847597 ps |
T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3500095251 |
|
|
May 23 12:48:16 PM PDT 24 |
May 23 12:48:18 PM PDT 24 |
16396330 ps |
T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3982297281 |
|
|
May 23 12:48:25 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
43399496 ps |
T126 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.460060773 |
|
|
May 23 12:48:13 PM PDT 24 |
May 23 12:48:16 PM PDT 24 |
285803390 ps |
T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1222605875 |
|
|
May 23 12:48:11 PM PDT 24 |
May 23 12:48:13 PM PDT 24 |
101144280 ps |
T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.57553940 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:28 PM PDT 24 |
1582697255 ps |
T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.584798282 |
|
|
May 23 12:48:48 PM PDT 24 |
May 23 12:48:50 PM PDT 24 |
15619439 ps |
T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4173841292 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:42 PM PDT 24 |
397450473 ps |
T988 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4179263193 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
25100995 ps |
T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1207281556 |
|
|
May 23 12:48:13 PM PDT 24 |
May 23 12:48:15 PM PDT 24 |
52038770 ps |
T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4210277226 |
|
|
May 23 12:48:14 PM PDT 24 |
May 23 12:48:18 PM PDT 24 |
34565667 ps |
T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1066244757 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:38 PM PDT 24 |
58180014 ps |
T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2681296136 |
|
|
May 23 12:48:47 PM PDT 24 |
May 23 12:48:48 PM PDT 24 |
12996976 ps |
T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.818298110 |
|
|
May 23 12:48:52 PM PDT 24 |
May 23 12:48:53 PM PDT 24 |
37531014 ps |
T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2535818106 |
|
|
May 23 12:48:49 PM PDT 24 |
May 23 12:48:53 PM PDT 24 |
395927859 ps |
T995 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1320617274 |
|
|
May 23 12:48:26 PM PDT 24 |
May 23 12:48:29 PM PDT 24 |
19788745 ps |
T127 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2045515377 |
|
|
May 23 12:48:52 PM PDT 24 |
May 23 12:48:55 PM PDT 24 |
166829454 ps |
T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3705974043 |
|
|
May 23 12:48:36 PM PDT 24 |
May 23 12:48:38 PM PDT 24 |
21389237 ps |
T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4265755556 |
|
|
May 23 12:48:26 PM PDT 24 |
May 23 12:48:30 PM PDT 24 |
337745599 ps |
T998 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.113659214 |
|
|
May 23 12:48:35 PM PDT 24 |
May 23 12:48:39 PM PDT 24 |
47105023 ps |
T999 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3504458714 |
|
|
May 23 12:48:38 PM PDT 24 |
May 23 12:48:42 PM PDT 24 |
64468794 ps |
T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.726087229 |
|
|
May 23 12:48:37 PM PDT 24 |
May 23 12:48:40 PM PDT 24 |
910012066 ps |
T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2083084589 |
|
|
May 23 12:48:15 PM PDT 24 |
May 23 12:48:16 PM PDT 24 |
20755443 ps |
T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1549673637 |
|
|
May 23 12:48:24 PM PDT 24 |
May 23 12:48:27 PM PDT 24 |
171253142 ps |