Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	91353838	1			T1	10514		T2	14576		T3	20000
instr_valid_dis	73753257	1			T1	10514		T2	14576		T3	20000
instr_en	12395789	1			T6	35244		T33	108236		T152	19060

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	4539168	1			T6	64166		T32	58270		T33	37284
sram_ifetch_valid_disable	75190546	1			T1	10514		T2	14576		T3	20000
sram_ifetch_enable	11624124	1			T6	160304		T32	176186		T33	50462

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	91353838	1			T1	10514		T2	14576		T3	20000
hw_debug_en_valid_off	74643814	1			T1	10514		T2	14576		T3	20000
hw_debug_en_on	11166768	1			T6	128308		T29	4686		T32	72750

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	75190546	1			T1	10514		T2	14576		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	68262351	1			T1	10514		T2	14576		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4913857	1			T6	27444		T33	92162		T121	13200
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2039094	1			T6	33598		T32	22650		T33	21802
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	896232	1			T33	21802		T152	21984		T25	39718
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	806274	1			T121	13996		T58	15176		T69	23520
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	1708906	1			T6	23224		T32	35620		T33	15482
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	641726	1			T33	15482		T24	5342		T152	56
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	750624	1			T152	19060		T58	18644		T69	8360
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4727574	1			T6	71396		T29	4686		T32	18248
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1878946	1			T29	4686		T33	21490		T24	60862
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2032280	1			T6	27374		T33	47484		T58	27154

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5464778	1			T6	7800		T33	16074		T121	29886
lc_exec_en	4730288	1			T6	33688		T32	18882		T33	24950
valid_exec_dis	72087500	1			T1	10514		T2	14576		T3	20000
invalid_exec_dis	16163292	1			T6	224470		T32	234456		T33	87746