ASSERT | PROPERTIES | SEQUENCES | |
Total | 657 | 0 | 20 |
Category 0 | 657 | 0 | 20 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 657 | 0 | 20 |
Severity 0 | 657 | 0 | 20 |
NUMBER | PERCENT | |
Total Number | 657 | 100.00 |
Uncovered | 3 | 0.46 |
Success | 654 | 99.54 |
Failure | 0 | 0.00 |
Incomplete | 1 | 0.15 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 20 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 20 | 100.00 |
First Matches | 20 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.FpvSecCmLcGateFsmCheck_A | 0 | 0 | 206805172 | 0 | 0 | 0 | |
tb.dut.FpvSecCmTlSramByteFsm_A | 0 | 0 | 206805172 | 0 | 0 | 0 | |
tb.dut.u_tlul_lc_gate.OutStandingOvfl_A | 0 | 0 | 206805172 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_prim_lc_sync.gen_flops.OutputDelay_A | 0 | 0 | 206805172 | 206711112 | 0 | 2283 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |