Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	89188024	1			T1	20060		T2	2530		T3	20000
instr_valid_dis	75311294	1			T1	20060		T2	2530		T3	20000
instr_en	9904596	1			T5	137430		T6	14400		T36	58554

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5301646	1			T5	22094		T36	17604		T42	94
sram_ifetch_valid_disable	72916596	1			T1	20060		T2	2530		T3	20000
sram_ifetch_enable	10969782	1			T5	83338		T6	45362		T36	206050

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	89188024	1			T1	20060		T2	2530		T3	20000
hw_debug_en_valid_off	72119608	1			T1	20060		T2	2530		T3	20000
hw_debug_en_on	11057000	1			T6	14352		T36	104856		T42	32208

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	72916596	1			T1	20060		T2	2530		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	66839274	1			T1	20060		T2	2530		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4436860	1			T5	54092		T36	45020		T16	92916
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2020628	1			T5	11374		T42	94		T16	2938
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1029786	1			T16	2938		T134	63032		T135	57244
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	567022	1			T42	94		T74	25216		T99	8736
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2240932	1			T36	17604		T16	54956		T41	59026
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1397530	1			T36	17604		T16	16342		T135	13104
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	521952	1			T16	27088		T74	29762		T75	6570
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4159308	1			T36	6296		T42	23096		T16	83238
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2056108	1			T42	23096		T16	39072		T173	45048
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1598982	1			T16	9046		T27	5640		T30	56510

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4013996	1			T5	83338		T6	14400		T36	13534
lc_exec_en	4656760	1			T6	14352		T36	80956		T42	9112
valid_exec_dis	71348658	1			T1	20060		T2	2530		T3	20000
invalid_exec_dis	16271428	1			T5	105432		T6	45362		T36	223654