Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.22 99.18 95.41 100.00 100.00 96.12 99.56 97.26


Total tests in report: 888
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.92 83.92 96.37 96.37 79.14 79.14 92.68 92.68 90.48 90.48 89.35 89.35 94.09 94.09 45.34 45.34 /workspace/coverage/default/46.sram_ctrl_executable.2047189350
88.00 4.08 97.52 1.16 82.73 3.60 94.79 2.11 100.00 9.52 92.82 3.47 94.39 0.30 53.75 8.41 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3804003245
90.53 2.53 97.77 0.25 86.45 3.72 95.43 0.64 100.00 0.00 93.29 0.46 96.45 2.07 64.35 10.60 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.983921328
92.66 2.13 98.27 0.50 88.25 1.80 95.57 0.14 100.00 0.00 94.21 0.93 96.45 0.00 75.87 11.52 /workspace/coverage/default/47.sram_ctrl_regwen.288687544
93.68 1.02 98.27 0.00 88.25 0.00 95.82 0.25 100.00 0.00 94.21 0.00 96.75 0.30 82.45 6.58 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1714482059
94.65 0.97 98.43 0.17 89.21 0.96 96.04 0.21 100.00 0.00 94.91 0.69 96.75 0.00 87.20 4.75 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.827807194
95.36 0.71 98.60 0.17 91.01 1.80 96.82 0.79 100.00 0.00 95.60 0.69 97.34 0.59 88.12 0.91 /workspace/coverage/default/1.sram_ctrl_sec_cm.204844607
96.02 0.67 98.60 0.00 91.25 0.24 98.96 2.14 100.00 0.00 96.06 0.46 97.34 0.00 89.95 1.83 /workspace/coverage/default/7.sram_ctrl_executable.2601047849
96.39 0.37 98.60 0.00 91.25 0.00 98.96 0.00 100.00 0.00 96.06 0.00 97.34 0.00 92.50 2.56 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3620619222
96.61 0.23 98.60 0.00 91.25 0.00 98.96 0.00 100.00 0.00 96.06 0.00 97.64 0.30 93.78 1.28 /workspace/coverage/default/29.sram_ctrl_regwen.744480031
96.77 0.16 98.60 0.00 91.25 0.00 99.04 0.07 100.00 0.00 96.06 0.00 98.67 1.03 93.78 0.00 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2825106364
96.92 0.15 98.60 0.00 91.25 0.00 99.04 0.00 100.00 0.00 96.06 0.00 99.56 0.89 93.97 0.18 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3642443750
97.07 0.14 98.84 0.25 91.37 0.12 99.07 0.04 100.00 0.00 96.30 0.23 99.56 0.00 94.33 0.37 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1421510626
97.20 0.13 98.84 0.00 91.37 0.00 99.07 0.00 100.00 0.00 96.30 0.00 99.56 0.00 95.25 0.91 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3519252661
97.32 0.12 98.84 0.00 91.49 0.12 99.07 0.00 100.00 0.00 96.30 0.00 99.56 0.00 95.98 0.73 /workspace/coverage/default/29.sram_ctrl_lc_escalation.650700281
97.43 0.11 98.93 0.08 91.49 0.00 99.79 0.71 100.00 0.00 96.30 0.00 99.56 0.00 95.98 0.00 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1575019931
97.53 0.10 99.17 0.25 91.85 0.36 99.86 0.07 100.00 0.00 96.30 0.00 99.56 0.00 95.98 0.00 /workspace/coverage/default/13.sram_ctrl_alert_test.3016655994
97.60 0.07 99.17 0.00 91.85 0.00 100.00 0.14 100.00 0.00 96.30 0.00 99.56 0.00 96.34 0.37 /workspace/coverage/default/9.sram_ctrl_regwen.2380010112
97.64 0.03 99.17 0.00 92.09 0.24 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.00 96.34 0.00 /workspace/coverage/default/12.sram_ctrl_lc_escalation.1970117599
97.66 0.03 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.00 96.53 0.18 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2626908465
97.69 0.03 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.00 96.71 0.18 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4179579074
97.72 0.03 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.00 96.89 0.18 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3704405904
97.74 0.03 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.00 97.07 0.18 /workspace/coverage/default/0.sram_ctrl_lc_escalation.1307280287
97.77 0.03 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.00 97.26 0.18 /workspace/coverage/default/10.sram_ctrl_executable.2264909449

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.985833735
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1707702892
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1989826508
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.489708325
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1567513344
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2853836508
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3000124607
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3967549916
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.305306717
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1206702919
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1409612459
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1258050030
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2547833367
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1514950323
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2854884690
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.972368813
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2493895746
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3159013646
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3477582166
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3250722493
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.844963173
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1687350298
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1550326261
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2473344539
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2040995520
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3122389124
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3432334930
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.730873179
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4014489709
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3368790190
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2028304184
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3113623603
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3317175187
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.535142905
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3829015216
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.9055038
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3613691895
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3321915753
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.12080595
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.228567269
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.246961779
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3962606854
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3164752515
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3430635128
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2212649476
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.101971765
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3460851420
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.155782299
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2149129230
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1628758640
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4039091944
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1532506722
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3539578877
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1950767531
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3192396279
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1128212422
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1091052305
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1397075806
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2542374064
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1248278290
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3232985806
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1709675692
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2706469279
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1712660820
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1075555022
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4036571347
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3315021692
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.849921612
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.476583895
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3008660212
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2280444343
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.767677697
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4232887743
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.360936996
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.745688320
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1841657181
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.56364365
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.460689038
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1867455345
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3859661756
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.835054302
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1064253885
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3199003838
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.896217616
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.153535671
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.407585548
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1256498325
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1726755462
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3735512265
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.405460317
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.366964937
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3586751326
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.898631915
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3456913640
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2175628060
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4200431785
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3661246856
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1641863642
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1555128250
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.36932308
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3364249448
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.253243170
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2610398541
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.742092413
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1560420023
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.942227082
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3466817035
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3617363902
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.196638596
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3875277162
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3894205740
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2280262356
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.709897234
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3215658541
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2150673683
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2665618478
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1947334823
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4191180618
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1876429056
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3166367249
/workspace/coverage/default/0.sram_ctrl_alert_test.3294184654
/workspace/coverage/default/0.sram_ctrl_bijection.3206468229
/workspace/coverage/default/0.sram_ctrl_executable.621672928
/workspace/coverage/default/0.sram_ctrl_max_throughput.1381474908
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1909485555
/workspace/coverage/default/0.sram_ctrl_mem_walk.442293506
/workspace/coverage/default/0.sram_ctrl_multiple_keys.774733270
/workspace/coverage/default/0.sram_ctrl_partial_access.507570228
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1411350221
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3529988798
/workspace/coverage/default/0.sram_ctrl_regwen.1997288080
/workspace/coverage/default/0.sram_ctrl_sec_cm.395500332
/workspace/coverage/default/0.sram_ctrl_smoke.3197340712
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1326473480
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3454229969
/workspace/coverage/default/1.sram_ctrl_alert_test.2672139357
/workspace/coverage/default/1.sram_ctrl_bijection.12213229
/workspace/coverage/default/1.sram_ctrl_executable.2496654411
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2128297207
/workspace/coverage/default/1.sram_ctrl_max_throughput.1845564309
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1570587642
/workspace/coverage/default/1.sram_ctrl_mem_walk.3531707598
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1499209550
/workspace/coverage/default/1.sram_ctrl_partial_access.2454221390
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.272682192
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2324441836
/workspace/coverage/default/1.sram_ctrl_regwen.1459712587
/workspace/coverage/default/1.sram_ctrl_smoke.4139441511
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.734618495
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1798558589
/workspace/coverage/default/10.sram_ctrl_alert_test.459526641
/workspace/coverage/default/10.sram_ctrl_bijection.1042388923
/workspace/coverage/default/10.sram_ctrl_lc_escalation.708209184
/workspace/coverage/default/10.sram_ctrl_max_throughput.2135054581
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1508490361
/workspace/coverage/default/10.sram_ctrl_mem_walk.2190335335
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2608948117
/workspace/coverage/default/10.sram_ctrl_partial_access.3336818823
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2643055364
/workspace/coverage/default/10.sram_ctrl_regwen.807494467
/workspace/coverage/default/10.sram_ctrl_smoke.1410231285
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1074416124
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.578729845
/workspace/coverage/default/11.sram_ctrl_alert_test.2769451850
/workspace/coverage/default/11.sram_ctrl_bijection.399168845
/workspace/coverage/default/11.sram_ctrl_executable.1578593564
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1772679619
/workspace/coverage/default/11.sram_ctrl_max_throughput.3297340891
/workspace/coverage/default/11.sram_ctrl_mem_walk.2706297171
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4103838297
/workspace/coverage/default/11.sram_ctrl_partial_access.1563019898
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2730402657
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3198873849
/workspace/coverage/default/11.sram_ctrl_regwen.257815023
/workspace/coverage/default/11.sram_ctrl_smoke.60972799
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2576820000
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2486265226
/workspace/coverage/default/12.sram_ctrl_alert_test.3928785657
/workspace/coverage/default/12.sram_ctrl_bijection.3731236170
/workspace/coverage/default/12.sram_ctrl_executable.3711177877
/workspace/coverage/default/12.sram_ctrl_max_throughput.3401837398
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2431923615
/workspace/coverage/default/12.sram_ctrl_mem_walk.2560915816
/workspace/coverage/default/12.sram_ctrl_multiple_keys.4084489845
/workspace/coverage/default/12.sram_ctrl_partial_access.1675773063
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1866577893
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2651278169
/workspace/coverage/default/12.sram_ctrl_regwen.756096793
/workspace/coverage/default/12.sram_ctrl_smoke.2285721365
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1217592087
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2073680346
/workspace/coverage/default/13.sram_ctrl_bijection.4086652775
/workspace/coverage/default/13.sram_ctrl_executable.3299234974
/workspace/coverage/default/13.sram_ctrl_lc_escalation.63950045
/workspace/coverage/default/13.sram_ctrl_max_throughput.333745545
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1801540537
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/workspace/coverage/default/5.sram_ctrl_smoke.2376218570
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1572378651
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3320307426
/workspace/coverage/default/6.sram_ctrl_alert_test.3577345648
/workspace/coverage/default/6.sram_ctrl_bijection.1718143862
/workspace/coverage/default/6.sram_ctrl_executable.2689786830
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4153243998
/workspace/coverage/default/6.sram_ctrl_max_throughput.406420485
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1869137803
/workspace/coverage/default/6.sram_ctrl_mem_walk.2208876269
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1056767884
/workspace/coverage/default/6.sram_ctrl_partial_access.3415453285
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2256225008
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1261540962
/workspace/coverage/default/6.sram_ctrl_regwen.2709119386
/workspace/coverage/default/6.sram_ctrl_smoke.2281844651
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.250834475
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.95538441
/workspace/coverage/default/7.sram_ctrl_alert_test.2775066939
/workspace/coverage/default/7.sram_ctrl_bijection.2860531598
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1924048742
/workspace/coverage/default/7.sram_ctrl_max_throughput.3125855168
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3979105141
/workspace/coverage/default/7.sram_ctrl_mem_walk.2983512859
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3752127124
/workspace/coverage/default/7.sram_ctrl_partial_access.1149624547
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2747647565
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2166507822
/workspace/coverage/default/7.sram_ctrl_regwen.3573437948
/workspace/coverage/default/7.sram_ctrl_smoke.895114896
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3890062463
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2240438620
/workspace/coverage/default/8.sram_ctrl_alert_test.3728780865
/workspace/coverage/default/8.sram_ctrl_bijection.4009865747
/workspace/coverage/default/8.sram_ctrl_executable.581986282
/workspace/coverage/default/8.sram_ctrl_lc_escalation.654120134
/workspace/coverage/default/8.sram_ctrl_max_throughput.3909077946
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1641112427
/workspace/coverage/default/8.sram_ctrl_mem_walk.1844437318
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2611485355
/workspace/coverage/default/8.sram_ctrl_partial_access.2709895786
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.681438064
/workspace/coverage/default/8.sram_ctrl_ram_cfg.187553876
/workspace/coverage/default/8.sram_ctrl_regwen.2101582933
/workspace/coverage/default/8.sram_ctrl_smoke.3316422643
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.268764626
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.193299904
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1322785059
/workspace/coverage/default/9.sram_ctrl_alert_test.218232713
/workspace/coverage/default/9.sram_ctrl_bijection.2779979835
/workspace/coverage/default/9.sram_ctrl_executable.703798310
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3532650704
/workspace/coverage/default/9.sram_ctrl_max_throughput.1815880885
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2984557476
/workspace/coverage/default/9.sram_ctrl_mem_walk.2323784185
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1607990379
/workspace/coverage/default/9.sram_ctrl_partial_access.160271578
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.74261377
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1552318943
/workspace/coverage/default/9.sram_ctrl_smoke.310594933
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.718309872
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1916326011



Total test records in report: 888
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.sram_ctrl_smoke.1410231285 May 28 02:13:54 PM PDT 24 May 28 02:16:32 PM PDT 24 2418778506 ps
T2 /workspace/coverage/default/25.sram_ctrl_smoke.1927744628 May 28 02:15:22 PM PDT 24 May 28 02:15:26 PM PDT 24 206695950 ps
T3 /workspace/coverage/default/15.sram_ctrl_max_throughput.99927029 May 28 02:14:09 PM PDT 24 May 28 02:15:17 PM PDT 24 273901033 ps
T10 /workspace/coverage/default/44.sram_ctrl_max_throughput.3516970425 May 28 02:18:44 PM PDT 24 May 28 02:18:49 PM PDT 24 91120388 ps
T4 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1002522876 May 28 02:13:31 PM PDT 24 May 28 02:18:24 PM PDT 24 79865014935 ps
T5 /workspace/coverage/default/46.sram_ctrl_executable.2047189350 May 28 02:19:04 PM PDT 24 May 28 02:25:57 PM PDT 24 10899883136 ps
T6 /workspace/coverage/default/36.sram_ctrl_executable.4066833638 May 28 02:17:19 PM PDT 24 May 28 02:21:18 PM PDT 24 6565632918 ps
T11 /workspace/coverage/default/22.sram_ctrl_max_throughput.1510621420 May 28 02:15:10 PM PDT 24 May 28 02:16:10 PM PDT 24 211761392 ps
T12 /workspace/coverage/default/44.sram_ctrl_partial_access.2190749080 May 28 02:18:27 PM PDT 24 May 28 02:18:35 PM PDT 24 132704291 ps
T13 /workspace/coverage/default/1.sram_ctrl_bijection.12213229 May 28 02:13:15 PM PDT 24 May 28 02:14:22 PM PDT 24 1104084858 ps
T17 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1421510626 May 28 02:18:51 PM PDT 24 May 28 02:23:18 PM PDT 24 22735358268 ps
T18 /workspace/coverage/default/42.sram_ctrl_smoke.234039902 May 28 02:18:07 PM PDT 24 May 28 02:20:18 PM PDT 24 281719161 ps
T19 /workspace/coverage/default/6.sram_ctrl_partial_access.3415453285 May 28 02:13:49 PM PDT 24 May 28 02:15:59 PM PDT 24 876349568 ps
T37 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.839206934 May 28 02:18:22 PM PDT 24 May 28 02:18:42 PM PDT 24 87986093 ps
T14 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3642443750 May 28 02:13:55 PM PDT 24 May 28 02:14:01 PM PDT 24 914841008 ps
T36 /workspace/coverage/default/48.sram_ctrl_executable.3952457501 May 28 02:19:26 PM PDT 24 May 28 02:33:07 PM PDT 24 22452805048 ps
T59 /workspace/coverage/default/17.sram_ctrl_partial_access.180138644 May 28 02:14:31 PM PDT 24 May 28 02:16:00 PM PDT 24 1128406085 ps
T15 /workspace/coverage/default/45.sram_ctrl_partial_access.2099278555 May 28 02:18:41 PM PDT 24 May 28 02:18:52 PM PDT 24 512710695 ps
T63 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.968698596 May 28 02:14:43 PM PDT 24 May 28 02:16:50 PM PDT 24 726108428 ps
T57 /workspace/coverage/default/36.sram_ctrl_partial_access.1844049898 May 28 02:17:05 PM PDT 24 May 28 02:18:09 PM PDT 24 2379211591 ps
T42 /workspace/coverage/default/4.sram_ctrl_executable.1968689707 May 28 02:13:31 PM PDT 24 May 28 02:18:11 PM PDT 24 1155601389 ps
T73 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.578729845 May 28 02:13:54 PM PDT 24 May 28 02:14:03 PM PDT 24 98708123 ps
T20 /workspace/coverage/default/39.sram_ctrl_alert_test.1621429846 May 28 02:17:53 PM PDT 24 May 28 02:17:56 PM PDT 24 35309986 ps
T16 /workspace/coverage/default/7.sram_ctrl_executable.2601047849 May 28 02:13:47 PM PDT 24 May 28 02:29:52 PM PDT 24 30470032755 ps
T96 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4039273205 May 28 02:14:57 PM PDT 24 May 28 02:18:02 PM PDT 24 4207407320 ps
T97 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1714482059 May 28 02:16:30 PM PDT 24 May 28 02:24:20 PM PDT 24 66141453054 ps
T27 /workspace/coverage/default/10.sram_ctrl_regwen.807494467 May 28 02:13:55 PM PDT 24 May 28 02:19:39 PM PDT 24 27144022046 ps
T76 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1909485555 May 28 02:13:17 PM PDT 24 May 28 02:13:24 PM PDT 24 707407544 ps
T77 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4127364249 May 28 02:13:35 PM PDT 24 May 28 02:13:41 PM PDT 24 70795781 ps
T68 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2546385672 May 28 02:15:21 PM PDT 24 May 28 02:15:26 PM PDT 24 229543459 ps
T78 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.4207676695 May 28 02:15:19 PM PDT 24 May 28 02:18:00 PM PDT 24 7188110481 ps
T28 /workspace/coverage/default/33.sram_ctrl_bijection.3921603456 May 28 02:16:43 PM PDT 24 May 28 02:17:02 PM PDT 24 2656308360 ps
T65 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1795409170 May 28 02:17:28 PM PDT 24 May 28 02:17:34 PM PDT 24 121702682 ps
T67 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2073680346 May 28 02:14:00 PM PDT 24 May 28 02:14:03 PM PDT 24 131395390 ps
T79 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.4107255752 May 28 02:15:10 PM PDT 24 May 28 02:15:17 PM PDT 24 576270223 ps
T80 /workspace/coverage/default/25.sram_ctrl_bijection.3090998871 May 28 02:15:27 PM PDT 24 May 28 02:16:09 PM PDT 24 1631118037 ps
T132 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2518028221 May 28 02:15:57 PM PDT 24 May 28 02:21:19 PM PDT 24 4495235995 ps
T21 /workspace/coverage/default/19.sram_ctrl_alert_test.1377251593 May 28 02:14:57 PM PDT 24 May 28 02:15:00 PM PDT 24 63919935 ps
T114 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1570587642 May 28 02:13:15 PM PDT 24 May 28 02:13:23 PM PDT 24 170901915 ps
T178 /workspace/coverage/default/40.sram_ctrl_mem_walk.682043032 May 28 02:17:53 PM PDT 24 May 28 02:17:59 PM PDT 24 285244710 ps
T7 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3804003245 May 28 02:18:51 PM PDT 24 May 28 02:18:58 PM PDT 24 2096780624 ps
T64 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.952029464 May 28 02:13:34 PM PDT 24 May 28 02:17:25 PM PDT 24 33830844424 ps
T183 /workspace/coverage/default/27.sram_ctrl_mem_walk.3077915229 May 28 02:15:56 PM PDT 24 May 28 02:16:03 PM PDT 24 917705326 ps
T177 /workspace/coverage/default/47.sram_ctrl_smoke.3306732653 May 28 02:19:01 PM PDT 24 May 28 02:19:04 PM PDT 24 57003809 ps
T66 /workspace/coverage/default/12.sram_ctrl_multiple_keys.4084489845 May 28 02:13:58 PM PDT 24 May 28 02:24:38 PM PDT 24 4080603386 ps
T180 /workspace/coverage/default/45.sram_ctrl_mem_walk.1994027743 May 28 02:18:52 PM PDT 24 May 28 02:19:00 PM PDT 24 2354138503 ps
T179 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1411350221 May 28 02:13:20 PM PDT 24 May 28 02:19:00 PM PDT 24 25080483800 ps
T41 /workspace/coverage/default/0.sram_ctrl_regwen.1997288080 May 28 02:13:15 PM PDT 24 May 28 02:29:41 PM PDT 24 6461553484 ps
T176 /workspace/coverage/default/8.sram_ctrl_bijection.4009865747 May 28 02:13:47 PM PDT 24 May 28 02:15:13 PM PDT 24 8077575278 ps
T115 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3183102375 May 28 02:19:02 PM PDT 24 May 28 02:19:09 PM PDT 24 174468220 ps
T169 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3620619222 May 28 02:13:54 PM PDT 24 May 28 02:22:42 PM PDT 24 40032480289 ps
T43 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2634348526 May 28 02:17:52 PM PDT 24 May 28 02:17:55 PM PDT 24 72146994 ps
T8 /workspace/coverage/default/2.sram_ctrl_lc_escalation.3552512218 May 28 02:13:36 PM PDT 24 May 28 02:13:41 PM PDT 24 209298254 ps
T175 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.460192854 May 28 02:18:39 PM PDT 24 May 28 02:22:59 PM PDT 24 33838889385 ps
T182 /workspace/coverage/default/13.sram_ctrl_mem_walk.512542519 May 28 02:14:04 PM PDT 24 May 28 02:14:16 PM PDT 24 451070679 ps
T116 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2194034132 May 28 02:14:45 PM PDT 24 May 28 02:14:54 PM PDT 24 634023939 ps
T44 /workspace/coverage/default/29.sram_ctrl_ram_cfg.730927351 May 28 02:16:06 PM PDT 24 May 28 02:16:08 PM PDT 24 48228690 ps
T30 /workspace/coverage/default/9.sram_ctrl_regwen.2380010112 May 28 02:13:53 PM PDT 24 May 28 02:22:25 PM PDT 24 6065304450 ps
T133 /workspace/coverage/default/33.sram_ctrl_multiple_keys.289201173 May 28 02:16:43 PM PDT 24 May 28 02:36:36 PM PDT 24 23242727389 ps
T98 /workspace/coverage/default/18.sram_ctrl_multiple_keys.1638790319 May 28 02:14:43 PM PDT 24 May 28 02:29:26 PM PDT 24 12048750110 ps
T74 /workspace/coverage/default/29.sram_ctrl_regwen.744480031 May 28 02:16:08 PM PDT 24 May 28 02:35:00 PM PDT 24 3634474922 ps
T165 /workspace/coverage/default/10.sram_ctrl_executable.2264909449 May 28 02:13:53 PM PDT 24 May 28 02:17:54 PM PDT 24 6376561985 ps
T184 /workspace/coverage/default/24.sram_ctrl_mem_walk.3743679663 May 28 02:15:20 PM PDT 24 May 28 02:15:31 PM PDT 24 152861735 ps
T45 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2166507822 May 28 02:13:48 PM PDT 24 May 28 02:13:52 PM PDT 24 144740447 ps
T181 /workspace/coverage/default/13.sram_ctrl_bijection.4086652775 May 28 02:14:03 PM PDT 24 May 28 02:15:23 PM PDT 24 4385056834 ps
T170 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2517017302 May 28 02:15:57 PM PDT 24 May 28 02:24:35 PM PDT 24 188110224398 ps
T31 /workspace/coverage/default/47.sram_ctrl_regwen.288687544 May 28 02:19:16 PM PDT 24 May 28 02:34:26 PM PDT 24 48617085183 ps
T185 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3041178714 May 28 02:16:07 PM PDT 24 May 28 02:25:28 PM PDT 24 42148427811 ps
T134 /workspace/coverage/default/12.sram_ctrl_executable.3711177877 May 28 02:13:56 PM PDT 24 May 28 02:39:34 PM PDT 24 14526638143 ps
T186 /workspace/coverage/default/40.sram_ctrl_bijection.918054664 May 28 02:17:55 PM PDT 24 May 28 02:18:57 PM PDT 24 5199546126 ps
T9 /workspace/coverage/default/29.sram_ctrl_lc_escalation.650700281 May 28 02:16:17 PM PDT 24 May 28 02:16:24 PM PDT 24 1161437260 ps
T187 /workspace/coverage/default/26.sram_ctrl_ram_cfg.42762717 May 28 02:15:41 PM PDT 24 May 28 02:15:43 PM PDT 24 26643069 ps
T135 /workspace/coverage/default/30.sram_ctrl_executable.3233635076 May 28 02:16:17 PM PDT 24 May 28 02:31:39 PM PDT 24 12525640109 ps
T188 /workspace/coverage/default/48.sram_ctrl_mem_walk.2090553381 May 28 02:19:24 PM PDT 24 May 28 02:19:31 PM PDT 24 845809495 ps
T189 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3015960174 May 28 02:13:38 PM PDT 24 May 28 02:33:46 PM PDT 24 14744865743 ps
T190 /workspace/coverage/default/49.sram_ctrl_mem_walk.681489655 May 28 02:19:36 PM PDT 24 May 28 02:19:43 PM PDT 24 1317061140 ps
T75 /workspace/coverage/default/35.sram_ctrl_regwen.503113252 May 28 02:17:11 PM PDT 24 May 28 02:28:12 PM PDT 24 12683645628 ps
T191 /workspace/coverage/default/41.sram_ctrl_mem_walk.2984993779 May 28 02:18:08 PM PDT 24 May 28 02:18:15 PM PDT 24 99368422 ps
T23 /workspace/coverage/default/33.sram_ctrl_alert_test.1291180234 May 28 02:16:53 PM PDT 24 May 28 02:16:55 PM PDT 24 33089281 ps
T192 /workspace/coverage/default/10.sram_ctrl_partial_access.3336818823 May 28 02:13:54 PM PDT 24 May 28 02:14:02 PM PDT 24 128447329 ps
T193 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3080264921 May 28 02:14:20 PM PDT 24 May 28 02:14:41 PM PDT 24 83894874 ps
T117 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.640953244 May 28 02:19:37 PM PDT 24 May 28 02:19:44 PM PDT 24 383116260 ps
T173 /workspace/coverage/default/29.sram_ctrl_executable.1789094354 May 28 02:16:08 PM PDT 24 May 28 02:30:28 PM PDT 24 23304295972 ps
T194 /workspace/coverage/default/34.sram_ctrl_mem_walk.3495508041 May 28 02:16:56 PM PDT 24 May 28 02:17:04 PM PDT 24 344571663 ps
T195 /workspace/coverage/default/36.sram_ctrl_ram_cfg.2916792965 May 28 02:17:20 PM PDT 24 May 28 02:17:22 PM PDT 24 54873175 ps
T29 /workspace/coverage/default/15.sram_ctrl_lc_escalation.595462223 May 28 02:14:08 PM PDT 24 May 28 02:14:15 PM PDT 24 814002441 ps
T196 /workspace/coverage/default/4.sram_ctrl_max_throughput.1562353290 May 28 02:13:32 PM PDT 24 May 28 02:15:47 PM PDT 24 405512737 ps
T99 /workspace/coverage/default/31.sram_ctrl_executable.602801553 May 28 02:16:29 PM PDT 24 May 28 02:30:49 PM PDT 24 4110826118 ps
T197 /workspace/coverage/default/47.sram_ctrl_partial_access.2066762132 May 28 02:19:04 PM PDT 24 May 28 02:19:10 PM PDT 24 262821885 ps
T168 /workspace/coverage/default/25.sram_ctrl_executable.3037686659 May 28 02:15:39 PM PDT 24 May 28 02:46:01 PM PDT 24 18526874526 ps
T100 /workspace/coverage/default/34.sram_ctrl_executable.2454547436 May 28 02:16:53 PM PDT 24 May 28 02:33:57 PM PDT 24 38498766880 ps
T198 /workspace/coverage/default/42.sram_ctrl_bijection.2953769856 May 28 02:18:06 PM PDT 24 May 28 02:19:12 PM PDT 24 10445821035 ps
T58 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1322785059 May 28 02:13:51 PM PDT 24 May 28 02:14:10 PM PDT 24 305099336 ps
T34 /workspace/coverage/default/0.sram_ctrl_lc_escalation.1307280287 May 28 02:13:17 PM PDT 24 May 28 02:13:29 PM PDT 24 2553282554 ps
T35 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3003462922 May 28 02:14:43 PM PDT 24 May 28 02:14:53 PM PDT 24 1764166908 ps
T22 /workspace/coverage/default/13.sram_ctrl_alert_test.3016655994 May 28 02:14:06 PM PDT 24 May 28 02:14:09 PM PDT 24 23075291 ps
T199 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1575019931 May 28 02:14:27 PM PDT 24 May 28 02:14:29 PM PDT 24 44296660 ps
T171 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2481858775 May 28 02:15:41 PM PDT 24 May 28 02:21:36 PM PDT 24 16581170652 ps
T200 /workspace/coverage/default/4.sram_ctrl_mem_walk.3487914865 May 28 02:13:33 PM PDT 24 May 28 02:13:40 PM PDT 24 306884304 ps
T201 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.193299904 May 28 02:13:49 PM PDT 24 May 28 02:14:48 PM PDT 24 116576253 ps
T202 /workspace/coverage/default/4.sram_ctrl_regwen.1677695520 May 28 02:13:32 PM PDT 24 May 28 02:28:22 PM PDT 24 11667094256 ps
T203 /workspace/coverage/default/47.sram_ctrl_executable.4258565257 May 28 02:19:04 PM PDT 24 May 28 02:34:16 PM PDT 24 52822256135 ps
T204 /workspace/coverage/default/0.sram_ctrl_smoke.3197340712 May 28 02:13:15 PM PDT 24 May 28 02:13:22 PM PDT 24 207054784 ps
T205 /workspace/coverage/default/21.sram_ctrl_bijection.562800631 May 28 02:14:57 PM PDT 24 May 28 02:15:54 PM PDT 24 3525760198 ps
T206 /workspace/coverage/default/35.sram_ctrl_executable.1426030674 May 28 02:17:05 PM PDT 24 May 28 02:20:11 PM PDT 24 3894963078 ps
T207 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2063279766 May 28 02:14:31 PM PDT 24 May 28 02:15:29 PM PDT 24 119985801 ps
T208 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.586745590 May 28 02:16:17 PM PDT 24 May 28 02:16:23 PM PDT 24 129484415 ps
T209 /workspace/coverage/default/35.sram_ctrl_smoke.2839796743 May 28 02:16:53 PM PDT 24 May 28 02:17:10 PM PDT 24 4103753656 ps
T210 /workspace/coverage/default/4.sram_ctrl_smoke.3277968435 May 28 02:13:34 PM PDT 24 May 28 02:14:13 PM PDT 24 388061442 ps
T118 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.788909378 May 28 02:15:39 PM PDT 24 May 28 02:15:46 PM PDT 24 1014183297 ps
T101 /workspace/coverage/default/22.sram_ctrl_lc_escalation.1041661282 May 28 02:15:08 PM PDT 24 May 28 02:15:17 PM PDT 24 2320322313 ps
T211 /workspace/coverage/default/2.sram_ctrl_regwen.2759338933 May 28 02:13:33 PM PDT 24 May 28 02:26:52 PM PDT 24 58986545928 ps
T212 /workspace/coverage/default/13.sram_ctrl_max_throughput.333745545 May 28 02:14:06 PM PDT 24 May 28 02:15:41 PM PDT 24 119557200 ps
T213 /workspace/coverage/default/2.sram_ctrl_smoke.1611232035 May 28 02:13:31 PM PDT 24 May 28 02:15:03 PM PDT 24 782710844 ps
T214 /workspace/coverage/default/40.sram_ctrl_smoke.656093359 May 28 02:17:51 PM PDT 24 May 28 02:17:59 PM PDT 24 407485890 ps
T215 /workspace/coverage/default/40.sram_ctrl_partial_access.1452254624 May 28 02:17:53 PM PDT 24 May 28 02:19:01 PM PDT 24 524012648 ps
T216 /workspace/coverage/default/30.sram_ctrl_bijection.1353113851 May 28 02:16:18 PM PDT 24 May 28 02:16:50 PM PDT 24 1316236466 ps
T217 /workspace/coverage/default/12.sram_ctrl_regwen.756096793 May 28 02:14:03 PM PDT 24 May 28 02:24:46 PM PDT 24 2883308773 ps
T218 /workspace/coverage/default/5.sram_ctrl_partial_access.183957396 May 28 02:13:33 PM PDT 24 May 28 02:15:52 PM PDT 24 1291282007 ps
T219 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3702569571 May 28 02:18:09 PM PDT 24 May 28 02:18:16 PM PDT 24 164285716 ps
T220 /workspace/coverage/default/19.sram_ctrl_smoke.810465868 May 28 02:14:44 PM PDT 24 May 28 02:15:17 PM PDT 24 576339614 ps
T221 /workspace/coverage/default/8.sram_ctrl_ram_cfg.187553876 May 28 02:13:54 PM PDT 24 May 28 02:13:58 PM PDT 24 29191442 ps
T222 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2640812856 May 28 02:18:07 PM PDT 24 May 28 02:24:02 PM PDT 24 6480270335 ps
T223 /workspace/coverage/default/28.sram_ctrl_mem_walk.1933175721 May 28 02:16:07 PM PDT 24 May 28 02:16:15 PM PDT 24 2267550020 ps
T224 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.556870186 May 28 02:16:53 PM PDT 24 May 28 02:21:44 PM PDT 24 38926490304 ps
T225 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2762140684 May 28 02:16:19 PM PDT 24 May 28 02:22:19 PM PDT 24 21450662007 ps
T174 /workspace/coverage/default/23.sram_ctrl_lc_escalation.646852472 May 28 02:15:09 PM PDT 24 May 28 02:15:14 PM PDT 24 261350563 ps
T226 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2486265226 May 28 02:13:58 PM PDT 24 May 28 02:14:20 PM PDT 24 381248957 ps
T227 /workspace/coverage/default/27.sram_ctrl_regwen.2490655162 May 28 02:15:57 PM PDT 24 May 28 02:30:00 PM PDT 24 3289315729 ps
T228 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.479055731 May 28 02:15:28 PM PDT 24 May 28 02:18:07 PM PDT 24 1328789917 ps
T229 /workspace/coverage/default/18.sram_ctrl_regwen.2179787414 May 28 02:14:44 PM PDT 24 May 28 02:24:44 PM PDT 24 2278005905 ps
T230 /workspace/coverage/default/34.sram_ctrl_smoke.1464530041 May 28 02:16:55 PM PDT 24 May 28 02:17:13 PM PDT 24 925469626 ps
T231 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3728769608 May 28 02:18:41 PM PDT 24 May 28 02:18:44 PM PDT 24 406296646 ps
T232 /workspace/coverage/default/39.sram_ctrl_smoke.2302060078 May 28 02:17:41 PM PDT 24 May 28 02:17:58 PM PDT 24 2434222848 ps
T233 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2644577345 May 28 02:17:18 PM PDT 24 May 28 02:22:53 PM PDT 24 13129904530 ps
T234 /workspace/coverage/default/47.sram_ctrl_mem_walk.2722896018 May 28 02:19:14 PM PDT 24 May 28 02:19:21 PM PDT 24 1029248425 ps
T172 /workspace/coverage/default/28.sram_ctrl_lc_escalation.921302170 May 28 02:15:55 PM PDT 24 May 28 02:16:00 PM PDT 24 380554940 ps
T102 /workspace/coverage/default/37.sram_ctrl_stress_all.805515890 May 28 02:17:21 PM PDT 24 May 28 02:35:30 PM PDT 24 21379330085 ps
T235 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3792247903 May 28 02:14:27 PM PDT 24 May 28 02:14:34 PM PDT 24 192403615 ps
T236 /workspace/coverage/default/13.sram_ctrl_multiple_keys.1109270404 May 28 02:14:00 PM PDT 24 May 28 02:32:29 PM PDT 24 86853237443 ps
T237 /workspace/coverage/default/22.sram_ctrl_executable.3459376964 May 28 02:15:10 PM PDT 24 May 28 02:16:03 PM PDT 24 9470935419 ps
T238 /workspace/coverage/default/34.sram_ctrl_max_throughput.2314043475 May 28 02:16:55 PM PDT 24 May 28 02:18:47 PM PDT 24 459630598 ps
T239 /workspace/coverage/default/16.sram_ctrl_max_throughput.2916144932 May 28 02:14:18 PM PDT 24 May 28 02:14:25 PM PDT 24 70983108 ps
T240 /workspace/coverage/default/8.sram_ctrl_multiple_keys.2611485355 May 28 02:13:48 PM PDT 24 May 28 02:22:25 PM PDT 24 15511252009 ps
T241 /workspace/coverage/default/28.sram_ctrl_bijection.3872607812 May 28 02:15:58 PM PDT 24 May 28 02:17:14 PM PDT 24 8783148416 ps
T242 /workspace/coverage/default/8.sram_ctrl_alert_test.3728780865 May 28 02:13:51 PM PDT 24 May 28 02:13:55 PM PDT 24 13516499 ps
T243 /workspace/coverage/default/23.sram_ctrl_multiple_keys.566637208 May 28 02:15:10 PM PDT 24 May 28 02:35:34 PM PDT 24 24611407039 ps
T244 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3698754146 May 28 02:15:09 PM PDT 24 May 28 02:16:29 PM PDT 24 127892071 ps
T245 /workspace/coverage/default/32.sram_ctrl_multiple_keys.2345768629 May 28 02:16:29 PM PDT 24 May 28 02:34:05 PM PDT 24 22734708608 ps
T246 /workspace/coverage/default/36.sram_ctrl_max_throughput.2295448253 May 28 02:17:04 PM PDT 24 May 28 02:17:07 PM PDT 24 38147731 ps
T103 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2312442153 May 28 02:13:33 PM PDT 24 May 28 02:25:40 PM PDT 24 3871301050 ps
T247 /workspace/coverage/default/36.sram_ctrl_mem_walk.329814218 May 28 02:17:23 PM PDT 24 May 28 02:17:33 PM PDT 24 141415109 ps
T32 /workspace/coverage/default/41.sram_ctrl_lc_escalation.1866456536 May 28 02:18:08 PM PDT 24 May 28 02:18:14 PM PDT 24 421011526 ps
T166 /workspace/coverage/default/2.sram_ctrl_executable.1379598590 May 28 02:13:33 PM PDT 24 May 28 02:30:41 PM PDT 24 19642217038 ps
T248 /workspace/coverage/default/31.sram_ctrl_multiple_keys.1677722982 May 28 02:16:18 PM PDT 24 May 28 02:21:16 PM PDT 24 1960285181 ps
T249 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1291219844 May 28 02:19:00 PM PDT 24 May 28 02:20:00 PM PDT 24 141439196 ps
T250 /workspace/coverage/default/4.sram_ctrl_alert_test.1387810153 May 28 02:13:33 PM PDT 24 May 28 02:13:36 PM PDT 24 19948908 ps
T251 /workspace/coverage/default/39.sram_ctrl_bijection.567711456 May 28 02:17:41 PM PDT 24 May 28 02:18:25 PM PDT 24 9919250212 ps
T252 /workspace/coverage/default/7.sram_ctrl_smoke.895114896 May 28 02:13:53 PM PDT 24 May 28 02:14:16 PM PDT 24 1511877376 ps
T253 /workspace/coverage/default/14.sram_ctrl_executable.2472188214 May 28 02:14:06 PM PDT 24 May 28 02:37:14 PM PDT 24 35237431577 ps
T254 /workspace/coverage/default/11.sram_ctrl_regwen.257815023 May 28 02:13:56 PM PDT 24 May 28 02:24:38 PM PDT 24 92462141972 ps
T33 /workspace/coverage/default/43.sram_ctrl_lc_escalation.3016670685 May 28 02:18:17 PM PDT 24 May 28 02:18:25 PM PDT 24 834543087 ps
T255 /workspace/coverage/default/21.sram_ctrl_smoke.702201004 May 28 02:14:57 PM PDT 24 May 28 02:16:12 PM PDT 24 2628303732 ps
T256 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1223860447 May 28 02:17:23 PM PDT 24 May 28 02:17:26 PM PDT 24 46116841 ps
T257 /workspace/coverage/default/20.sram_ctrl_ram_cfg.823571057 May 28 02:14:57 PM PDT 24 May 28 02:15:00 PM PDT 24 30396768 ps
T258 /workspace/coverage/default/35.sram_ctrl_ram_cfg.460915427 May 28 02:17:08 PM PDT 24 May 28 02:17:10 PM PDT 24 87915319 ps
T259 /workspace/coverage/default/44.sram_ctrl_alert_test.1464003267 May 28 02:18:38 PM PDT 24 May 28 02:18:40 PM PDT 24 22162093 ps
T260 /workspace/coverage/default/5.sram_ctrl_lc_escalation.171339326 May 28 02:13:34 PM PDT 24 May 28 02:13:42 PM PDT 24 644015195 ps
T261 /workspace/coverage/default/21.sram_ctrl_ram_cfg.3563293680 May 28 02:14:59 PM PDT 24 May 28 02:15:01 PM PDT 24 28131231 ps
T262 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1641112427 May 28 02:13:50 PM PDT 24 May 28 02:13:58 PM PDT 24 195207520 ps
T263 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2262155343 May 28 02:16:56 PM PDT 24 May 28 02:16:59 PM PDT 24 102057263 ps
T264 /workspace/coverage/default/9.sram_ctrl_max_throughput.1815880885 May 28 02:13:51 PM PDT 24 May 28 02:13:55 PM PDT 24 110524482 ps
T265 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.4205496031 May 28 02:16:30 PM PDT 24 May 28 02:20:53 PM PDT 24 16669633835 ps
T266 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1628202939 May 28 02:15:41 PM PDT 24 May 28 02:15:46 PM PDT 24 402503628 ps
T267 /workspace/coverage/default/4.sram_ctrl_bijection.3275241232 May 28 02:13:34 PM PDT 24 May 28 02:13:54 PM PDT 24 247963027 ps
T268 /workspace/coverage/default/14.sram_ctrl_max_throughput.3298960231 May 28 02:14:13 PM PDT 24 May 28 02:14:16 PM PDT 24 168314709 ps
T269 /workspace/coverage/default/22.sram_ctrl_alert_test.83551954 May 28 02:15:10 PM PDT 24 May 28 02:15:13 PM PDT 24 57730514 ps
T270 /workspace/coverage/default/32.sram_ctrl_max_throughput.3847001685 May 28 02:16:29 PM PDT 24 May 28 02:16:59 PM PDT 24 336610795 ps
T271 /workspace/coverage/default/18.sram_ctrl_partial_access.4240152831 May 28 02:14:44 PM PDT 24 May 28 02:16:06 PM PDT 24 167868626 ps
T272 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2617258510 May 28 02:15:21 PM PDT 24 May 28 02:15:26 PM PDT 24 420296256 ps
T273 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1599246453 May 28 02:13:33 PM PDT 24 May 28 02:16:21 PM PDT 24 6219275003 ps
T274 /workspace/coverage/default/19.sram_ctrl_bijection.3393615536 May 28 02:14:43 PM PDT 24 May 28 02:15:11 PM PDT 24 6894903747 ps
T275 /workspace/coverage/default/7.sram_ctrl_mem_walk.2983512859 May 28 02:13:50 PM PDT 24 May 28 02:13:59 PM PDT 24 241657035 ps
T276 /workspace/coverage/default/24.sram_ctrl_max_throughput.105443159 May 28 02:15:23 PM PDT 24 May 28 02:17:05 PM PDT 24 132599211 ps
T277 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3468747319 May 28 02:14:27 PM PDT 24 May 28 02:14:52 PM PDT 24 87861727 ps
T278 /workspace/coverage/default/6.sram_ctrl_max_throughput.406420485 May 28 02:13:50 PM PDT 24 May 28 02:16:23 PM PDT 24 512851119 ps
T279 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2307020168 May 28 02:13:49 PM PDT 24 May 28 02:13:55 PM PDT 24 101633887 ps
T280 /workspace/coverage/default/38.sram_ctrl_lc_escalation.627153266 May 28 02:17:29 PM PDT 24 May 28 02:17:39 PM PDT 24 596342059 ps
T281 /workspace/coverage/default/19.sram_ctrl_ram_cfg.857851978 May 28 02:14:43 PM PDT 24 May 28 02:14:48 PM PDT 24 29780205 ps
T282 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.4015911496 May 28 02:16:31 PM PDT 24 May 28 02:23:49 PM PDT 24 132733381675 ps
T283 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1170099578 May 28 02:16:43 PM PDT 24 May 28 02:16:48 PM PDT 24 95616798 ps
T284 /workspace/coverage/default/13.sram_ctrl_regwen.3013285778 May 28 02:14:05 PM PDT 24 May 28 02:22:52 PM PDT 24 24850516822 ps
T24 /workspace/coverage/default/1.sram_ctrl_sec_cm.204844607 May 28 02:13:14 PM PDT 24 May 28 02:13:19 PM PDT 24 3087378762 ps
T48 /workspace/coverage/default/42.sram_ctrl_partial_access.3110993749 May 28 02:18:07 PM PDT 24 May 28 02:19:43 PM PDT 24 730102956 ps
T49 /workspace/coverage/default/45.sram_ctrl_alert_test.2387444912 May 28 02:18:51 PM PDT 24 May 28 02:18:53 PM PDT 24 14104242 ps
T50 /workspace/coverage/default/26.sram_ctrl_lc_escalation.544573680 May 28 02:15:38 PM PDT 24 May 28 02:15:46 PM PDT 24 2002757679 ps
T51 /workspace/coverage/default/39.sram_ctrl_executable.1264190450 May 28 02:17:41 PM PDT 24 May 28 02:20:53 PM PDT 24 5125711306 ps
T52 /workspace/coverage/default/43.sram_ctrl_smoke.269169975 May 28 02:18:15 PM PDT 24 May 28 02:18:20 PM PDT 24 59740744 ps
T53 /workspace/coverage/default/47.sram_ctrl_bijection.2138377070 May 28 02:19:03 PM PDT 24 May 28 02:19:50 PM PDT 24 3037582065 ps
T54 /workspace/coverage/default/30.sram_ctrl_lc_escalation.2321772047 May 28 02:16:18 PM PDT 24 May 28 02:16:26 PM PDT 24 739581826 ps
T55 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2747647565 May 28 02:13:46 PM PDT 24 May 28 02:20:04 PM PDT 24 26432438998 ps
T56 /workspace/coverage/default/22.sram_ctrl_smoke.2609267312 May 28 02:15:09 PM PDT 24 May 28 02:16:00 PM PDT 24 184053994 ps
T285 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1869137803 May 28 02:13:49 PM PDT 24 May 28 02:13:58 PM PDT 24 148858946 ps
T286 /workspace/coverage/default/10.sram_ctrl_alert_test.459526641 May 28 02:13:56 PM PDT 24 May 28 02:14:00 PM PDT 24 75973633 ps
T287 /workspace/coverage/default/21.sram_ctrl_regwen.1803560708 May 28 02:14:58 PM PDT 24 May 28 02:20:31 PM PDT 24 13014452617 ps
T288 /workspace/coverage/default/48.sram_ctrl_smoke.3887731400 May 28 02:19:16 PM PDT 24 May 28 02:19:21 PM PDT 24 168787995 ps
T104 /workspace/coverage/default/8.sram_ctrl_executable.581986282 May 28 02:13:49 PM PDT 24 May 28 02:38:11 PM PDT 24 51126237523 ps
T289 /workspace/coverage/default/23.sram_ctrl_executable.2194239227 May 28 02:15:11 PM PDT 24 May 28 02:27:44 PM PDT 24 1730914866 ps
T290 /workspace/coverage/default/7.sram_ctrl_bijection.2860531598 May 28 02:13:50 PM PDT 24 May 28 02:14:42 PM PDT 24 798786677 ps
T291 /workspace/coverage/default/0.sram_ctrl_max_throughput.1381474908 May 28 02:13:16 PM PDT 24 May 28 02:13:24 PM PDT 24 51780106 ps
T38 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2287102325 May 28 02:17:56 PM PDT 24 May 28 02:18:08 PM PDT 24 543950767 ps
T87 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2580773873 May 28 02:17:54 PM PDT 24 May 28 02:20:41 PM PDT 24 426851429 ps
T88 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2243040101 May 28 02:15:39 PM PDT 24 May 28 02:27:18 PM PDT 24 2515581574 ps
T89 /workspace/coverage/default/0.sram_ctrl_mem_walk.442293506 May 28 02:13:14 PM PDT 24 May 28 02:13:19 PM PDT 24 155772672 ps
T90 /workspace/coverage/default/21.sram_ctrl_alert_test.304865602 May 28 02:15:00 PM PDT 24 May 28 02:15:01 PM PDT 24 20708175 ps
T91 /workspace/coverage/default/41.sram_ctrl_executable.759666875 May 28 02:18:06 PM PDT 24 May 28 02:20:55 PM PDT 24 890225554 ps
T92 /workspace/coverage/default/10.sram_ctrl_bijection.1042388923 May 28 02:13:53 PM PDT 24 May 28 02:14:30 PM PDT 24 7259722380 ps
T93 /workspace/coverage/default/29.sram_ctrl_max_throughput.2462075368 May 28 02:16:08 PM PDT 24 May 28 02:16:49 PM PDT 24 88562112 ps
T94 /workspace/coverage/default/35.sram_ctrl_multiple_keys.1162082866 May 28 02:16:54 PM PDT 24 May 28 02:32:02 PM PDT 24 13434755506 ps
T95 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3214242452 May 28 02:17:53 PM PDT 24 May 28 02:23:04 PM PDT 24 27948755467 ps
T292 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3529160838 May 28 02:19:13 PM PDT 24 May 28 02:20:01 PM PDT 24 168169103 ps
T293 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.95924249 May 28 02:15:55 PM PDT 24 May 28 02:16:01 PM PDT 24 971465746 ps
T294 /workspace/coverage/default/9.sram_ctrl_smoke.310594933 May 28 02:13:50 PM PDT 24 May 28 02:14:01 PM PDT 24 1727408568 ps
T295 /workspace/coverage/default/41.sram_ctrl_bijection.1718584048 May 28 02:18:06 PM PDT 24 May 28 02:18:34 PM PDT 24 2828964508 ps
T296 /workspace/coverage/default/28.sram_ctrl_max_throughput.2340593069 May 28 02:15:55 PM PDT 24 May 28 02:16:36 PM PDT 24 352962437 ps
T297 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1468872108 May 28 02:14:17 PM PDT 24 May 28 02:16:04 PM PDT 24 4706546403 ps
T298 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2227604311 May 28 02:13:33 PM PDT 24 May 28 02:13:40 PM PDT 24 127337573 ps
T39 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.263899208 May 28 02:13:35 PM PDT 24 May 28 02:13:45 PM PDT 24 244398780 ps
T299 /workspace/coverage/default/41.sram_ctrl_alert_test.796193138 May 28 02:18:05 PM PDT 24 May 28 02:18:06 PM PDT 24 11027314 ps
T300 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.229601597 May 28 02:18:51 PM PDT 24 May 28 02:18:56 PM PDT 24 379578675 ps
T301 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2022253705 May 28 02:16:10 PM PDT 24 May 28 02:20:00 PM PDT 24 58113501053 ps
T302 /workspace/coverage/default/11.sram_ctrl_alert_test.2769451850 May 28 02:13:58 PM PDT 24 May 28 02:14:01 PM PDT 24 40393607 ps
T303 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3604345504 May 28 02:15:56 PM PDT 24 May 28 02:17:25 PM PDT 24 536842528 ps
T304 /workspace/coverage/default/13.sram_ctrl_lc_escalation.63950045 May 28 02:13:58 PM PDT 24 May 28 02:14:07 PM PDT 24 501903761 ps
T305 /workspace/coverage/default/43.sram_ctrl_ram_cfg.3301092544 May 28 02:18:28 PM PDT 24 May 28 02:18:30 PM PDT 24 48259532 ps
T306 /workspace/coverage/default/31.sram_ctrl_ram_cfg.3592028956 May 28 02:16:30 PM PDT 24 May 28 02:16:33 PM PDT 24 29224478 ps
T307 /workspace/coverage/default/42.sram_ctrl_regwen.572646833 May 28 02:18:17 PM PDT 24 May 28 02:30:37 PM PDT 24 17133963234 ps
T308 /workspace/coverage/default/3.sram_ctrl_lc_escalation.680117562 May 28 02:13:34 PM PDT 24 May 28 02:13:42 PM PDT 24 406675641 ps
T309 /workspace/coverage/default/12.sram_ctrl_smoke.2285721365 May 28 02:13:57 PM PDT 24 May 28 02:15:15 PM PDT 24 6477602644 ps
T310 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1261540962 May 28 02:13:48 PM PDT 24 May 28 02:13:51 PM PDT 24 26380276 ps
T311 /workspace/coverage/default/29.sram_ctrl_mem_walk.167788540 May 28 02:16:16 PM PDT 24 May 28 02:16:22 PM PDT 24 76352648 ps
T312 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1350842700 May 28 02:13:32 PM PDT 24 May 28 02:13:40 PM PDT 24 383780938 ps
T313 /workspace/coverage/default/39.sram_ctrl_multiple_keys.2823039246 May 28 02:17:41 PM PDT 24 May 28 02:28:23 PM PDT 24 9792694390 ps
T314 /workspace/coverage/default/29.sram_ctrl_alert_test.1097386851 May 28 02:16:17 PM PDT 24 May 28 02:16:19 PM PDT 24 20594123 ps
T315 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2889811544 May 28 02:15:08 PM PDT 24 May 28 02:17:53 PM PDT 24 5793073646 ps
T316 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1927890279 May 28 02:17:18 PM PDT 24 May 28 02:20:01 PM PDT 24 586347199 ps
T317 /workspace/coverage/default/4.sram_ctrl_ram_cfg.859490144 May 28 02:13:34 PM PDT 24 May 28 02:13:38 PM PDT 24 34872820 ps
T318 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3742182087 May 28 02:14:10 PM PDT 24 May 28 02:17:55 PM PDT 24 9690506752 ps
T319 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1270357319 May 28 02:14:28 PM PDT 24 May 28 02:14:35 PM PDT 24 348038372 ps
T320 /workspace/coverage/default/15.sram_ctrl_bijection.3984686126 May 28 02:14:20 PM PDT 24 May 28 02:14:46 PM PDT 24 3975710590 ps
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