Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	25432982	1			T1	9103		T2	1153		T3	10000
triple_byte_access	2134268	1			T1	179		T2	24		T4	27227
halfword_access	3205745	1			T1	277		T2	26		T4	41236
byte_access	4283840	1			T1	373		T2	50		T4	54983
zero_access	1077535	1			T1	98		T2	12		T4	13634

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18022627

1

T1

4917

T2

619

T3

5002

auto[1]

18111743

1

T1

5113

T2

646

T3

4998

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	12676107	1			T1	4471		T2	560		T3	5002
auto[0]	triple_byte_access	1064469	1			T1	92		T2	12		T4	13624
auto[0]	halfword_access	1598811	1			T1	126		T2	13		T4	20812
auto[0]	byte_access	2140577	1			T1	174		T2	26		T4	27564
auto[0]	zero_access	542663	1			T1	54		T2	8		T4	6832
auto[1]	word_access	12756875	1			T1	4632		T2	593		T3	4998
auto[1]	triple_byte_access	1069799	1			T1	87		T2	12		T4	13603
auto[1]	halfword_access	1606934	1			T1	151		T2	13		T4	20424
auto[1]	byte_access	2143263	1			T1	199		T2	24		T4	27419
auto[1]	zero_access	534872	1			T1	44		T2	4		T4	6802