Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	92381302	1			T1	86016		T2	86016		T3	6142
instr_valid_dis	74203351	1			T1	86016		T2	86016		T3	6142
instr_en	12343662	1			T15	142600		T13	291102		T148	211134

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5878578	1			T15	8884		T22	86646		T148	83580
sram_ifetch_valid_disable	74158670	1			T1	86016		T2	86016		T3	6142
sram_ifetch_enable	12344054	1			T15	136534		T22	14672		T13	201410

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	92381302	1			T1	86016		T2	86016		T3	6142
hw_debug_en_valid_off	73486752	1			T1	86016		T2	86016		T3	6142
hw_debug_en_on	12525748	1			T15	42764		T22	99736		T13	113876

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	74158670	1			T1	86016		T2	86016		T3	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	67133911	1			T1	86016		T2	86016		T3	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4732546	1			T15	35152		T13	89692		T148	79472
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2180610	1			T15	8884		T22	33188		T148	98
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1096024	1			T15	8884		T22	18904		T148	98
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	809436	1			T122	7850		T77	12022		T123	13782
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2489536	1			T22	42562		T51	8872		T58	50802
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	967594	1			T22	28154		T123	11014		T151	77008
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1064738	1			T58	50802		T77	29106		T67	36142
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4905844	1			T15	14676		T22	48812		T13	44888
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2115920	1			T22	48812		T148	27000		T23	70306
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2011708	1			T15	14676		T13	44888		T148	48224

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5231186	1			T15	107448		T13	201410		T148	98124
lc_exec_en	5130368	1			T15	28088		T22	8362		T13	68988
valid_exec_dis	71347712	1			T1	86016		T2	86016		T3	6142
invalid_exec_dis	18222632	1			T15	145418		T22	101318		T13	201410