Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.24 99.18 95.41 100.00 100.00 96.12 99.56 97.44


Total tests in report: 888
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
78.55 78.55 95.71 95.71 73.50 73.50 85.57 85.57 71.43 71.43 87.27 87.27 94.53 94.53 41.86 41.86 /workspace/coverage/default/36.sram_ctrl_lc_escalation.1415447953
87.50 8.95 98.02 2.31 81.65 8.15 87.14 1.57 100.00 28.57 93.98 6.71 94.68 0.15 57.04 15.17 /workspace/coverage/default/36.sram_ctrl_regwen.2481410562
91.25 3.75 98.51 0.50 85.49 3.84 87.86 0.71 100.00 0.00 94.44 0.46 96.01 1.33 76.42 19.38 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3145568415
93.75 2.51 98.76 0.25 88.49 3.00 97.57 9.71 100.00 0.00 94.68 0.23 96.16 0.15 80.62 4.20 /workspace/coverage/default/38.sram_ctrl_executable.3518598510
94.75 1.00 99.09 0.33 90.77 2.28 99.07 1.50 100.00 0.00 96.06 1.39 96.75 0.59 81.54 0.91 /workspace/coverage/default/0.sram_ctrl_sec_cm.726273306
95.55 0.80 99.09 0.00 91.37 0.60 99.07 0.00 100.00 0.00 96.06 0.00 97.34 0.59 85.92 4.39 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1769366055
96.28 0.73 99.09 0.00 91.37 0.00 99.07 0.00 100.00 0.00 96.06 0.00 97.49 0.15 90.86 4.94 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3074875820
96.59 0.31 99.09 0.00 91.37 0.00 99.07 0.00 100.00 0.00 96.06 0.00 97.49 0.00 93.05 2.19 /workspace/coverage/default/1.sram_ctrl_regwen.2513916128
96.77 0.18 99.09 0.00 91.37 0.00 99.07 0.00 100.00 0.00 96.06 0.00 97.49 0.00 94.33 1.28 /workspace/coverage/default/43.sram_ctrl_executable.839817562
96.93 0.16 99.09 0.00 91.37 0.00 99.07 0.00 100.00 0.00 96.30 0.23 98.38 0.89 94.33 0.00 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2390168406
97.09 0.16 99.09 0.00 91.37 0.00 99.14 0.07 100.00 0.00 96.30 0.00 99.41 1.03 94.33 0.00 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2243698690
97.25 0.16 99.09 0.00 91.37 0.00 99.14 0.00 100.00 0.00 96.30 0.00 99.41 0.00 95.43 1.10 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3580786360
97.36 0.11 99.17 0.08 91.37 0.00 99.86 0.71 100.00 0.00 96.30 0.00 99.41 0.00 95.43 0.00 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3273630754
97.47 0.10 99.17 0.00 91.37 0.00 99.86 0.00 100.00 0.00 96.30 0.00 99.41 0.00 96.16 0.73 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1808125172
97.57 0.10 99.17 0.00 91.37 0.00 99.86 0.00 100.00 0.00 96.30 0.00 99.41 0.00 96.89 0.73 /workspace/coverage/default/13.sram_ctrl_executable.1174545756
97.65 0.08 99.17 0.00 91.49 0.12 99.93 0.07 100.00 0.00 96.30 0.00 99.41 0.00 97.26 0.37 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3561653656
97.71 0.06 99.17 0.00 91.85 0.36 100.00 0.07 100.00 0.00 96.30 0.00 99.41 0.00 97.26 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.3390723661
97.75 0.03 99.17 0.00 92.09 0.24 100.00 0.00 100.00 0.00 96.30 0.00 99.41 0.00 97.26 0.00 /workspace/coverage/default/1.sram_ctrl_lc_escalation.883537647
97.77 0.03 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.41 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3222836876
97.79 0.02 99.17 0.00 92.09 0.00 100.00 0.00 100.00 0.00 96.30 0.00 99.56 0.15 97.44 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4150583579

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3965492941
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1965817097
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1812668143
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1923363641
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1080733133
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4194755028
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1914635611
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4229283336
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.475549426
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1772774145
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2116451421
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3920554658
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1083541188
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1311784353
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3696159242
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.376215142
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1813041473
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.91449207
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3128473365
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.15916628
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2772818911
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3128126122
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3278284840
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3050074854
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3368532864
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1436774382
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4136538877
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1382748458
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.494645636
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1744815313
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.611587230
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3937455557
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1491548388
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4052410920
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1479867591
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1434877126
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.82096131
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1321810313
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3760102125
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4015939736
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.693632495
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3774592970
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.601388206
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.359377188
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2025389948
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4227430409
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.740808321
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1719464872
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3671713422
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2887847042
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2123240093
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.878707069
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3314417063
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1915698096
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2296044504
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2068346439
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.611823576
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1826904466
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1724257620
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.490111576
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2118066657
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2065739424
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1086821215
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1681175624
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2484634813
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2913387686
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3225814366
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1106720163
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2185022640
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3182229602
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1438408648
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2242787302
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.740938530
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.544453218
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3222140009
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.498774325
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1639145262
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1482616705
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3931416611
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3658852774
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3698554709
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.860409390
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2673959068
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1931652980
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1147833385
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2877039517
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.449403621
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1675640195
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1921703654
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1121645397
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.968036291
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1194431650
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3279498108
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1920231855
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1808401143
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1082764930
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.466800868
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3587878709
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2237329804
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.576682141
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.232687181
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.862775549
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.955824410
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3252021249
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1156452980
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1661595685
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.741926414
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1170241514
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2337110329
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.763105410
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2710239169
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3237136138
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.468364761
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3806816697
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1440838088
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2781835365
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1830941180
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1041962545
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3263955751
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.941748087
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1737131515
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1596721911
/workspace/coverage/default/0.sram_ctrl_bijection.1358015635
/workspace/coverage/default/0.sram_ctrl_executable.911146050
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1950971312
/workspace/coverage/default/0.sram_ctrl_max_throughput.743081534
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.4284203105
/workspace/coverage/default/0.sram_ctrl_mem_walk.3172643319
/workspace/coverage/default/0.sram_ctrl_multiple_keys.536286776
/workspace/coverage/default/0.sram_ctrl_partial_access.1990144299
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1709334391
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3480441954
/workspace/coverage/default/0.sram_ctrl_regwen.4211743873
/workspace/coverage/default/0.sram_ctrl_smoke.740382541
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1185901331
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2392301743
/workspace/coverage/default/1.sram_ctrl_alert_test.3491594146
/workspace/coverage/default/1.sram_ctrl_bijection.2466233754
/workspace/coverage/default/1.sram_ctrl_executable.553570168
/workspace/coverage/default/1.sram_ctrl_max_throughput.1351308880
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.4100147587
/workspace/coverage/default/1.sram_ctrl_mem_walk.4024754959
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1831364335
/workspace/coverage/default/1.sram_ctrl_partial_access.2035112235
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3939712800
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3531350231
/workspace/coverage/default/1.sram_ctrl_sec_cm.3754603743
/workspace/coverage/default/1.sram_ctrl_smoke.1186554216
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1134264106
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2313214030
/workspace/coverage/default/10.sram_ctrl_alert_test.749060849
/workspace/coverage/default/10.sram_ctrl_bijection.2510435060
/workspace/coverage/default/10.sram_ctrl_executable.2352620640
/workspace/coverage/default/10.sram_ctrl_lc_escalation.143543535
/workspace/coverage/default/10.sram_ctrl_max_throughput.4077733524
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2095193030
/workspace/coverage/default/10.sram_ctrl_mem_walk.59462624
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3396971298
/workspace/coverage/default/10.sram_ctrl_partial_access.667948414
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3167081500
/workspace/coverage/default/10.sram_ctrl_ram_cfg.4267331724
/workspace/coverage/default/10.sram_ctrl_regwen.1682544766
/workspace/coverage/default/10.sram_ctrl_smoke.4208735289
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3786590759
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2344462190
/workspace/coverage/default/11.sram_ctrl_alert_test.3379152340
/workspace/coverage/default/11.sram_ctrl_bijection.738915415
/workspace/coverage/default/11.sram_ctrl_executable.2268689601
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3222234752
/workspace/coverage/default/11.sram_ctrl_max_throughput.3170476670
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3579919079
/workspace/coverage/default/11.sram_ctrl_mem_walk.1420113654
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2521309882
/workspace/coverage/default/11.sram_ctrl_partial_access.1633296223
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1021704165
/workspace/coverage/default/11.sram_ctrl_regwen.3461402387
/workspace/coverage/default/11.sram_ctrl_smoke.896396433
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.875795704
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2615035080
/workspace/coverage/default/12.sram_ctrl_alert_test.83885860
/workspace/coverage/default/12.sram_ctrl_bijection.3223944026
/workspace/coverage/default/12.sram_ctrl_executable.21228226
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2404495816
/workspace/coverage/default/12.sram_ctrl_max_throughput.2663230575
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.81278018
/workspace/coverage/default/12.sram_ctrl_mem_walk.1767001819
/workspace/coverage/default/12.sram_ctrl_multiple_keys.4180309457
/workspace/coverage/default/12.sram_ctrl_partial_access.421504818
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1165732590
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1065913855
/workspace/coverage/default/12.sram_ctrl_smoke.2337249286
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.4193087834
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1177877036
/workspace/coverage/default/13.sram_ctrl_alert_test.2194369063
/workspace/coverage/default/13.sram_ctrl_bijection.740332185
/workspace/coverage/default/13.sram_ctrl_lc_escalation.4196059500
/workspace/coverage/default/13.sram_ctrl_max_throughput.3577513924
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2067221104
/workspace/coverage/default/13.sram_ctrl_mem_walk.1025587224
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3488264503
/workspace/coverage/default/13.sram_ctrl_partial_access.1779612177
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.4175163350
/workspace/coverage/default/13.sram_ctrl_ram_cfg.788567900
/workspace/coverage/default/13.sram_ctrl_regwen.2753760874
/workspace/coverage/default/13.sram_ctrl_smoke.2581438561
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3843978103
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2705225016
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/workspace/coverage/default/6.sram_ctrl_lc_escalation.1963963128
/workspace/coverage/default/6.sram_ctrl_max_throughput.3863629720
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3954439562
/workspace/coverage/default/6.sram_ctrl_mem_walk.3212164360
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1752195202
/workspace/coverage/default/6.sram_ctrl_partial_access.314615405
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4022342873
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3021866204
/workspace/coverage/default/6.sram_ctrl_regwen.1664224814
/workspace/coverage/default/6.sram_ctrl_smoke.2645812112
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.309332622
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2230259042
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3799619861
/workspace/coverage/default/7.sram_ctrl_alert_test.3136998384
/workspace/coverage/default/7.sram_ctrl_bijection.4260608822
/workspace/coverage/default/7.sram_ctrl_executable.1142562837
/workspace/coverage/default/7.sram_ctrl_lc_escalation.660446505
/workspace/coverage/default/7.sram_ctrl_max_throughput.275863393
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3675766327
/workspace/coverage/default/7.sram_ctrl_mem_walk.499140014
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2321416015
/workspace/coverage/default/7.sram_ctrl_partial_access.3847969830
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3558798929
/workspace/coverage/default/7.sram_ctrl_ram_cfg.402864004
/workspace/coverage/default/7.sram_ctrl_regwen.4054100130
/workspace/coverage/default/7.sram_ctrl_smoke.81756842
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1173099784
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1080989151
/workspace/coverage/default/8.sram_ctrl_alert_test.3502109073
/workspace/coverage/default/8.sram_ctrl_bijection.985737321
/workspace/coverage/default/8.sram_ctrl_executable.1336634269
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1599994752
/workspace/coverage/default/8.sram_ctrl_max_throughput.3286962546
/workspace/coverage/default/8.sram_ctrl_mem_walk.3899385276
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1783185348
/workspace/coverage/default/8.sram_ctrl_partial_access.2222760969
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2370223928
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2044103428
/workspace/coverage/default/8.sram_ctrl_regwen.1322712584
/workspace/coverage/default/8.sram_ctrl_smoke.3413212895
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.732188689
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.722599994
/workspace/coverage/default/9.sram_ctrl_alert_test.2091142612
/workspace/coverage/default/9.sram_ctrl_bijection.2530593554
/workspace/coverage/default/9.sram_ctrl_executable.650522323
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2822092951
/workspace/coverage/default/9.sram_ctrl_max_throughput.2729741836
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.823079950
/workspace/coverage/default/9.sram_ctrl_mem_walk.1565012717
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1335847837
/workspace/coverage/default/9.sram_ctrl_partial_access.1604509253
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.426835388
/workspace/coverage/default/9.sram_ctrl_ram_cfg.664085680
/workspace/coverage/default/9.sram_ctrl_regwen.2314099934
/workspace/coverage/default/9.sram_ctrl_smoke.343986783
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.709134702
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.428981914



Total test records in report: 888
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.sram_ctrl_bijection.2530593554 May 30 03:28:04 PM PDT 24 May 30 03:29:11 PM PDT 24 2136751005 ps
T2 /workspace/coverage/default/4.sram_ctrl_bijection.4293497281 May 30 03:27:30 PM PDT 24 May 30 03:28:41 PM PDT 24 12113044821 ps
T3 /workspace/coverage/default/1.sram_ctrl_mem_walk.4024754959 May 30 03:27:07 PM PDT 24 May 30 03:27:13 PM PDT 24 1199597290 ps
T9 /workspace/coverage/default/7.sram_ctrl_smoke.81756842 May 30 03:27:39 PM PDT 24 May 30 03:27:56 PM PDT 24 634280435 ps
T4 /workspace/coverage/default/36.sram_ctrl_lc_escalation.1415447953 May 30 03:31:58 PM PDT 24 May 30 03:32:04 PM PDT 24 724287834 ps
T10 /workspace/coverage/default/42.sram_ctrl_partial_access.4013721689 May 30 03:32:41 PM PDT 24 May 30 03:32:54 PM PDT 24 1142674473 ps
T5 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.239847409 May 30 03:31:46 PM PDT 24 May 30 03:33:20 PM PDT 24 537515232 ps
T11 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1075039960 May 30 03:32:33 PM PDT 24 May 30 03:32:36 PM PDT 24 28812027 ps
T12 /workspace/coverage/default/36.sram_ctrl_mem_walk.2349041387 May 30 03:31:56 PM PDT 24 May 30 03:32:07 PM PDT 24 689564769 ps
T6 /workspace/coverage/default/19.sram_ctrl_partial_access.258083272 May 30 03:29:23 PM PDT 24 May 30 03:30:54 PM PDT 24 821437208 ps
T15 /workspace/coverage/default/38.sram_ctrl_executable.3518598510 May 30 03:32:12 PM PDT 24 May 30 03:41:21 PM PDT 24 4906206384 ps
T42 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3189774754 May 30 03:33:09 PM PDT 24 May 30 03:38:39 PM PDT 24 5399455481 ps
T7 /workspace/coverage/default/39.sram_ctrl_lc_escalation.4084138651 May 30 03:32:18 PM PDT 24 May 30 03:32:26 PM PDT 24 620045998 ps
T45 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3351186560 May 30 03:28:42 PM PDT 24 May 30 03:30:46 PM PDT 24 286525419 ps
T46 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1434064732 May 30 03:30:40 PM PDT 24 May 30 03:30:47 PM PDT 24 595652492 ps
T53 /workspace/coverage/default/41.sram_ctrl_max_throughput.771694128 May 30 03:32:40 PM PDT 24 May 30 03:35:08 PM PDT 24 145653302 ps
T44 /workspace/coverage/default/0.sram_ctrl_partial_access.1990144299 May 30 03:26:57 PM PDT 24 May 30 03:27:01 PM PDT 24 251821197 ps
T22 /workspace/coverage/default/2.sram_ctrl_regwen.3039070306 May 30 03:27:17 PM PDT 24 May 30 03:37:24 PM PDT 24 1395299101 ps
T29 /workspace/coverage/default/28.sram_ctrl_ram_cfg.4017086760 May 30 03:30:52 PM PDT 24 May 30 03:30:54 PM PDT 24 33474690 ps
T13 /workspace/coverage/default/36.sram_ctrl_regwen.2481410562 May 30 03:31:58 PM PDT 24 May 30 03:43:48 PM PDT 24 14069120760 ps
T85 /workspace/coverage/default/39.sram_ctrl_max_throughput.3420733869 May 30 03:32:18 PM PDT 24 May 30 03:33:47 PM PDT 24 428482327 ps
T47 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3222073795 May 30 03:30:45 PM PDT 24 May 30 03:34:29 PM PDT 24 5732582535 ps
T86 /workspace/coverage/default/16.sram_ctrl_bijection.214935634 May 30 03:28:59 PM PDT 24 May 30 03:29:21 PM PDT 24 1981764493 ps
T54 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3597697787 May 30 03:29:22 PM PDT 24 May 30 03:31:10 PM PDT 24 288573258 ps
T52 /workspace/coverage/default/45.sram_ctrl_bijection.1000278853 May 30 03:33:11 PM PDT 24 May 30 03:33:29 PM PDT 24 1076092258 ps
T55 /workspace/coverage/default/2.sram_ctrl_bijection.4074042774 May 30 03:27:05 PM PDT 24 May 30 03:28:32 PM PDT 24 4588838269 ps
T75 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4284203105 May 30 03:27:07 PM PDT 24 May 30 03:27:11 PM PDT 24 186292369 ps
T148 /workspace/coverage/default/43.sram_ctrl_executable.839817562 May 30 03:32:51 PM PDT 24 May 30 03:49:54 PM PDT 24 18472193894 ps
T16 /workspace/coverage/default/27.sram_ctrl_alert_test.2050144355 May 30 03:30:43 PM PDT 24 May 30 03:30:44 PM PDT 24 19081775 ps
T17 /workspace/coverage/default/41.sram_ctrl_alert_test.3346327117 May 30 03:32:41 PM PDT 24 May 30 03:32:43 PM PDT 24 14428845 ps
T30 /workspace/coverage/default/4.sram_ctrl_ram_cfg.30767050 May 30 03:27:30 PM PDT 24 May 30 03:27:32 PM PDT 24 199493964 ps
T120 /workspace/coverage/default/40.sram_ctrl_multiple_keys.1563790899 May 30 03:32:32 PM PDT 24 May 30 04:00:10 PM PDT 24 5464504662 ps
T163 /workspace/coverage/default/3.sram_ctrl_mem_walk.276365339 May 30 03:27:28 PM PDT 24 May 30 03:27:36 PM PDT 24 454060445 ps
T159 /workspace/coverage/default/10.sram_ctrl_mem_walk.59462624 May 30 03:28:16 PM PDT 24 May 30 03:28:23 PM PDT 24 230739041 ps
T14 /workspace/coverage/default/38.sram_ctrl_smoke.1488461886 May 30 03:32:10 PM PDT 24 May 30 03:33:24 PM PDT 24 1135109941 ps
T51 /workspace/coverage/default/26.sram_ctrl_regwen.1146036794 May 30 03:30:32 PM PDT 24 May 30 03:45:53 PM PDT 24 51950815569 ps
T165 /workspace/coverage/default/26.sram_ctrl_ram_cfg.757272996 May 30 03:30:32 PM PDT 24 May 30 03:30:34 PM PDT 24 82773588 ps
T158 /workspace/coverage/default/39.sram_ctrl_mem_walk.3893937941 May 30 03:32:19 PM PDT 24 May 30 03:32:28 PM PDT 24 351902920 ps
T76 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2390168406 May 30 03:27:56 PM PDT 24 May 30 03:28:03 PM PDT 24 191612286 ps
T113 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3074875820 May 30 03:28:16 PM PDT 24 May 30 03:33:01 PM PDT 24 11999246083 ps
T164 /workspace/coverage/default/25.sram_ctrl_partial_access.3528337375 May 30 03:30:21 PM PDT 24 May 30 03:31:56 PM PDT 24 408714691 ps
T166 /workspace/coverage/default/29.sram_ctrl_max_throughput.445481613 May 30 03:30:51 PM PDT 24 May 30 03:31:02 PM PDT 24 228761295 ps
T157 /workspace/coverage/default/19.sram_ctrl_multiple_keys.4078617066 May 30 03:29:23 PM PDT 24 May 30 03:53:27 PM PDT 24 65554506356 ps
T167 /workspace/coverage/default/35.sram_ctrl_bijection.2065152435 May 30 03:31:45 PM PDT 24 May 30 03:32:13 PM PDT 24 2016533309 ps
T96 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2067221104 May 30 03:28:38 PM PDT 24 May 30 03:28:46 PM PDT 24 571359012 ps
T18 /workspace/coverage/default/14.sram_ctrl_alert_test.934234420 May 30 03:28:48 PM PDT 24 May 30 03:28:50 PM PDT 24 12525858 ps
T168 /workspace/coverage/default/33.sram_ctrl_max_throughput.1316255105 May 30 03:31:31 PM PDT 24 May 30 03:31:34 PM PDT 24 43130219 ps
T23 /workspace/coverage/default/37.sram_ctrl_regwen.2141801021 May 30 03:32:12 PM PDT 24 May 30 03:43:44 PM PDT 24 2031547658 ps
T114 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.621511631 May 30 03:28:49 PM PDT 24 May 30 03:37:07 PM PDT 24 65746658153 ps
T115 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3381715753 May 30 03:29:34 PM PDT 24 May 30 03:32:54 PM PDT 24 13610456090 ps
T162 /workspace/coverage/default/6.sram_ctrl_partial_access.314615405 May 30 03:27:44 PM PDT 24 May 30 03:29:11 PM PDT 24 2987290851 ps
T169 /workspace/coverage/default/28.sram_ctrl_mem_walk.1958046336 May 30 03:30:51 PM PDT 24 May 30 03:31:03 PM PDT 24 1198995585 ps
T116 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4022767088 May 30 03:31:33 PM PDT 24 May 30 03:36:08 PM PDT 24 17572494005 ps
T170 /workspace/coverage/default/38.sram_ctrl_ram_cfg.237608411 May 30 03:32:18 PM PDT 24 May 30 03:32:21 PM PDT 24 120082011 ps
T171 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3273630754 May 30 03:28:58 PM PDT 24 May 30 03:29:00 PM PDT 24 87369752 ps
T117 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2370223928 May 30 03:27:57 PM PDT 24 May 30 03:34:21 PM PDT 24 13907776542 ps
T172 /workspace/coverage/default/6.sram_ctrl_smoke.2645812112 May 30 03:27:41 PM PDT 24 May 30 03:27:54 PM PDT 24 714217077 ps
T161 /workspace/coverage/default/31.sram_ctrl_bijection.293592475 May 30 03:31:14 PM PDT 24 May 30 03:32:20 PM PDT 24 11524079744 ps
T153 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3314928410 May 30 03:31:04 PM PDT 24 May 30 03:45:42 PM PDT 24 43224292549 ps
T173 /workspace/coverage/default/13.sram_ctrl_max_throughput.3577513924 May 30 03:28:39 PM PDT 24 May 30 03:29:11 PM PDT 24 89504319 ps
T118 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3561653656 May 30 03:30:51 PM PDT 24 May 30 03:35:14 PM PDT 24 4461577602 ps
T174 /workspace/coverage/default/35.sram_ctrl_smoke.3335068384 May 30 03:31:45 PM PDT 24 May 30 03:31:56 PM PDT 24 545130927 ps
T97 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3921600457 May 30 03:30:34 PM PDT 24 May 30 03:30:39 PM PDT 24 382392260 ps
T58 /workspace/coverage/default/6.sram_ctrl_regwen.1664224814 May 30 03:27:40 PM PDT 24 May 30 03:34:04 PM PDT 24 8170279888 ps
T175 /workspace/coverage/default/27.sram_ctrl_bijection.2989444541 May 30 03:30:33 PM PDT 24 May 30 03:31:44 PM PDT 24 9860213412 ps
T98 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2546970135 May 30 03:31:15 PM PDT 24 May 30 03:31:20 PM PDT 24 397316096 ps
T176 /workspace/coverage/default/30.sram_ctrl_smoke.233151679 May 30 03:31:01 PM PDT 24 May 30 03:31:04 PM PDT 24 117525526 ps
T177 /workspace/coverage/default/47.sram_ctrl_partial_access.2491335364 May 30 03:33:29 PM PDT 24 May 30 03:35:36 PM PDT 24 232563719 ps
T99 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2144194136 May 30 03:28:47 PM PDT 24 May 30 03:28:54 PM PDT 24 342620374 ps
T8 /workspace/coverage/default/8.sram_ctrl_lc_escalation.1599994752 May 30 03:27:49 PM PDT 24 May 30 03:27:58 PM PDT 24 2193355904 ps
T119 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.336491745 May 30 03:27:38 PM PDT 24 May 30 03:33:53 PM PDT 24 65362893554 ps
T24 /workspace/coverage/default/15.sram_ctrl_lc_escalation.1401955696 May 30 03:28:48 PM PDT 24 May 30 03:28:54 PM PDT 24 348152962 ps
T178 /workspace/coverage/default/49.sram_ctrl_mem_walk.3465185662 May 30 03:33:49 PM PDT 24 May 30 03:33:55 PM PDT 24 72845437 ps
T160 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2806761078 May 30 03:33:47 PM PDT 24 May 30 03:36:53 PM PDT 24 11363633169 ps
T59 /workspace/coverage/default/35.sram_ctrl_lc_escalation.1550958839 May 30 03:31:46 PM PDT 24 May 30 03:31:48 PM PDT 24 143826099 ps
T152 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3718413817 May 30 03:29:43 PM PDT 24 May 30 03:37:04 PM PDT 24 31034869883 ps
T179 /workspace/coverage/default/30.sram_ctrl_alert_test.3494946645 May 30 03:31:13 PM PDT 24 May 30 03:31:15 PM PDT 24 40596033 ps
T180 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2943644312 May 30 03:31:02 PM PDT 24 May 30 03:32:14 PM PDT 24 755346772 ps
T19 /workspace/coverage/default/0.sram_ctrl_sec_cm.726273306 May 30 03:27:07 PM PDT 24 May 30 03:27:11 PM PDT 24 386219633 ps
T33 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.467012352 May 30 03:33:31 PM PDT 24 May 30 03:39:53 PM PDT 24 83477863376 ps
T34 /workspace/coverage/default/12.sram_ctrl_smoke.2337249286 May 30 03:28:28 PM PDT 24 May 30 03:28:34 PM PDT 24 738001316 ps
T35 /workspace/coverage/default/22.sram_ctrl_bijection.3092596446 May 30 03:29:53 PM PDT 24 May 30 03:31:06 PM PDT 24 8827500699 ps
T36 /workspace/coverage/default/45.sram_ctrl_partial_access.1865481413 May 30 03:33:10 PM PDT 24 May 30 03:34:43 PM PDT 24 455267577 ps
T37 /workspace/coverage/default/3.sram_ctrl_regwen.3477177175 May 30 03:27:30 PM PDT 24 May 30 03:46:44 PM PDT 24 42652155200 ps
T38 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2095193030 May 30 03:28:14 PM PDT 24 May 30 03:28:19 PM PDT 24 56849135 ps
T39 /workspace/coverage/default/32.sram_ctrl_bijection.1819131919 May 30 03:31:24 PM PDT 24 May 30 03:32:35 PM PDT 24 6731373333 ps
T40 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2946861912 May 30 03:28:57 PM PDT 24 May 30 03:29:02 PM PDT 24 109384222 ps
T41 /workspace/coverage/default/17.sram_ctrl_smoke.1727105999 May 30 03:29:12 PM PDT 24 May 30 03:29:29 PM PDT 24 245359727 ps
T181 /workspace/coverage/default/13.sram_ctrl_alert_test.2194369063 May 30 03:28:39 PM PDT 24 May 30 03:28:41 PM PDT 24 20136464 ps
T182 /workspace/coverage/default/30.sram_ctrl_max_throughput.645399858 May 30 03:31:02 PM PDT 24 May 30 03:32:28 PM PDT 24 210856858 ps
T121 /workspace/coverage/default/42.sram_ctrl_multiple_keys.256561551 May 30 03:32:42 PM PDT 24 May 30 03:51:52 PM PDT 24 19509097742 ps
T141 /workspace/coverage/default/44.sram_ctrl_lc_escalation.286001704 May 30 03:32:58 PM PDT 24 May 30 03:33:02 PM PDT 24 343166848 ps
T183 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4181798407 May 30 03:27:28 PM PDT 24 May 30 03:34:46 PM PDT 24 16739606792 ps
T184 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1614510361 May 30 03:30:32 PM PDT 24 May 30 03:31:27 PM PDT 24 131651508 ps
T185 /workspace/coverage/default/27.sram_ctrl_smoke.88782500 May 30 03:30:31 PM PDT 24 May 30 03:30:55 PM PDT 24 9515425026 ps
T122 /workspace/coverage/default/5.sram_ctrl_executable.3708769318 May 30 03:27:45 PM PDT 24 May 30 03:33:53 PM PDT 24 31510943593 ps
T186 /workspace/coverage/default/10.sram_ctrl_smoke.4208735289 May 30 03:28:16 PM PDT 24 May 30 03:28:30 PM PDT 24 939598415 ps
T187 /workspace/coverage/default/19.sram_ctrl_mem_walk.273215026 May 30 03:29:34 PM PDT 24 May 30 03:29:46 PM PDT 24 1547481168 ps
T188 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3786590759 May 30 03:28:16 PM PDT 24 May 30 03:30:12 PM PDT 24 9529558310 ps
T77 /workspace/coverage/default/1.sram_ctrl_regwen.2513916128 May 30 03:27:07 PM PDT 24 May 30 03:32:32 PM PDT 24 120578079551 ps
T189 /workspace/coverage/default/5.sram_ctrl_mem_walk.1248134297 May 30 03:27:38 PM PDT 24 May 30 03:27:50 PM PDT 24 175443144 ps
T78 /workspace/coverage/default/46.sram_ctrl_multiple_keys.1855784304 May 30 03:33:22 PM PDT 24 May 30 03:57:38 PM PDT 24 116119456219 ps
T190 /workspace/coverage/default/29.sram_ctrl_mem_walk.826466999 May 30 03:31:03 PM PDT 24 May 30 03:31:09 PM PDT 24 103547961 ps
T191 /workspace/coverage/default/44.sram_ctrl_mem_walk.1761356962 May 30 03:33:09 PM PDT 24 May 30 03:33:16 PM PDT 24 607378431 ps
T192 /workspace/coverage/default/49.sram_ctrl_ram_cfg.1954554706 May 30 03:33:49 PM PDT 24 May 30 03:33:51 PM PDT 24 29625823 ps
T193 /workspace/coverage/default/42.sram_ctrl_mem_walk.696497376 May 30 03:32:50 PM PDT 24 May 30 03:32:56 PM PDT 24 1282321996 ps
T194 /workspace/coverage/default/49.sram_ctrl_max_throughput.592270263 May 30 03:33:51 PM PDT 24 May 30 03:33:54 PM PDT 24 69433383 ps
T26 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3145568415 May 30 03:28:39 PM PDT 24 May 30 03:30:13 PM PDT 24 466319537 ps
T25 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2767765309 May 30 03:33:29 PM PDT 24 May 30 03:33:38 PM PDT 24 2145129857 ps
T67 /workspace/coverage/default/5.sram_ctrl_regwen.1511974745 May 30 03:27:40 PM PDT 24 May 30 03:42:57 PM PDT 24 51178556648 ps
T68 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.419245501 May 30 03:27:43 PM PDT 24 May 30 03:27:50 PM PDT 24 187588787 ps
T69 /workspace/coverage/default/0.sram_ctrl_alert_test.3390723661 May 30 03:27:06 PM PDT 24 May 30 03:27:08 PM PDT 24 12338349 ps
T70 /workspace/coverage/default/31.sram_ctrl_smoke.1070405117 May 30 03:31:15 PM PDT 24 May 30 03:31:32 PM PDT 24 912912422 ps
T71 /workspace/coverage/default/14.sram_ctrl_mem_walk.3321366822 May 30 03:28:53 PM PDT 24 May 30 03:29:00 PM PDT 24 331156242 ps
T72 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2803166314 May 30 03:32:49 PM PDT 24 May 30 03:33:40 PM PDT 24 643203996 ps
T73 /workspace/coverage/default/42.sram_ctrl_max_throughput.37538684 May 30 03:32:48 PM PDT 24 May 30 03:35:02 PM PDT 24 148094852 ps
T74 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2158343673 May 30 03:32:51 PM PDT 24 May 30 03:32:53 PM PDT 24 89739560 ps
T195 /workspace/coverage/default/29.sram_ctrl_ram_cfg.1482537172 May 30 03:31:01 PM PDT 24 May 30 03:31:03 PM PDT 24 82147212 ps
T196 /workspace/coverage/default/29.sram_ctrl_smoke.2014155587 May 30 03:30:52 PM PDT 24 May 30 03:33:32 PM PDT 24 737339418 ps
T197 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1155513462 May 30 03:32:41 PM PDT 24 May 30 03:32:48 PM PDT 24 603540280 ps
T123 /workspace/coverage/default/13.sram_ctrl_executable.1174545756 May 30 03:28:41 PM PDT 24 May 30 03:45:32 PM PDT 24 12893352883 ps
T79 /workspace/coverage/default/19.sram_ctrl_regwen.2030836297 May 30 03:29:35 PM PDT 24 May 30 03:50:08 PM PDT 24 3733162116 ps
T198 /workspace/coverage/default/22.sram_ctrl_max_throughput.2425243239 May 30 03:29:55 PM PDT 24 May 30 03:30:33 PM PDT 24 99185746 ps
T199 /workspace/coverage/default/15.sram_ctrl_max_throughput.3366160801 May 30 03:28:47 PM PDT 24 May 30 03:29:07 PM PDT 24 177578155 ps
T200 /workspace/coverage/default/49.sram_ctrl_partial_access.1840724690 May 30 03:33:50 PM PDT 24 May 30 03:33:57 PM PDT 24 127943191 ps
T201 /workspace/coverage/default/37.sram_ctrl_bijection.304195064 May 30 03:31:55 PM PDT 24 May 30 03:33:02 PM PDT 24 1093054109 ps
T202 /workspace/coverage/default/44.sram_ctrl_multiple_keys.4024902103 May 30 03:33:02 PM PDT 24 May 30 03:43:28 PM PDT 24 3284297810 ps
T154 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2048708254 May 30 03:31:15 PM PDT 24 May 30 03:40:18 PM PDT 24 91392408665 ps
T203 /workspace/coverage/default/45.sram_ctrl_ram_cfg.2801565317 May 30 03:33:21 PM PDT 24 May 30 03:33:24 PM PDT 24 90365950 ps
T204 /workspace/coverage/default/20.sram_ctrl_bijection.4183456120 May 30 03:29:33 PM PDT 24 May 30 03:31:05 PM PDT 24 5623509101 ps
T151 /workspace/coverage/default/49.sram_ctrl_executable.552448533 May 30 03:33:51 PM PDT 24 May 30 03:47:29 PM PDT 24 77001431510 ps
T205 /workspace/coverage/default/29.sram_ctrl_bijection.4152561509 May 30 03:30:51 PM PDT 24 May 30 03:31:15 PM PDT 24 4565314159 ps
T206 /workspace/coverage/default/18.sram_ctrl_executable.3523485770 May 30 03:29:23 PM PDT 24 May 30 03:57:27 PM PDT 24 176894451895 ps
T207 /workspace/coverage/default/22.sram_ctrl_alert_test.2513763592 May 30 03:29:54 PM PDT 24 May 30 03:29:56 PM PDT 24 40270311 ps
T208 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2364801282 May 30 03:31:31 PM PDT 24 May 30 03:35:23 PM PDT 24 9561832739 ps
T209 /workspace/coverage/default/7.sram_ctrl_max_throughput.275863393 May 30 03:27:41 PM PDT 24 May 30 03:27:56 PM PDT 24 85116464 ps
T210 /workspace/coverage/default/8.sram_ctrl_bijection.985737321 May 30 03:27:50 PM PDT 24 May 30 03:28:27 PM PDT 24 5989907575 ps
T211 /workspace/coverage/default/48.sram_ctrl_ram_cfg.98893160 May 30 03:33:38 PM PDT 24 May 30 03:33:41 PM PDT 24 66043271 ps
T212 /workspace/coverage/default/10.sram_ctrl_max_throughput.4077733524 May 30 03:28:21 PM PDT 24 May 30 03:30:59 PM PDT 24 136556558 ps
T213 /workspace/coverage/default/8.sram_ctrl_alert_test.3502109073 May 30 03:28:05 PM PDT 24 May 30 03:28:07 PM PDT 24 23528233 ps
T214 /workspace/coverage/default/5.sram_ctrl_max_throughput.3501703376 May 30 03:27:43 PM PDT 24 May 30 03:27:46 PM PDT 24 44926187 ps
T215 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2786469891 May 30 03:30:21 PM PDT 24 May 30 03:30:28 PM PDT 24 164819587 ps
T216 /workspace/coverage/default/32.sram_ctrl_smoke.873595617 May 30 03:31:22 PM PDT 24 May 30 03:32:00 PM PDT 24 422918471 ps
T217 /workspace/coverage/default/46.sram_ctrl_max_throughput.1278289988 May 30 03:33:20 PM PDT 24 May 30 03:33:28 PM PDT 24 99720620 ps
T218 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.316573482 May 30 03:31:56 PM PDT 24 May 30 03:32:02 PM PDT 24 156835725 ps
T219 /workspace/coverage/default/9.sram_ctrl_alert_test.2091142612 May 30 03:28:15 PM PDT 24 May 30 03:28:17 PM PDT 24 12084913 ps
T220 /workspace/coverage/default/45.sram_ctrl_max_throughput.1855567670 May 30 03:33:10 PM PDT 24 May 30 03:33:56 PM PDT 24 471106204 ps
T221 /workspace/coverage/default/45.sram_ctrl_smoke.425445261 May 30 03:33:11 PM PDT 24 May 30 03:33:15 PM PDT 24 59538789 ps
T222 /workspace/coverage/default/34.sram_ctrl_regwen.1407595056 May 30 03:31:45 PM PDT 24 May 30 03:58:19 PM PDT 24 66096278157 ps
T223 /workspace/coverage/default/43.sram_ctrl_multiple_keys.3931680664 May 30 03:32:51 PM PDT 24 May 30 03:37:02 PM PDT 24 4610598078 ps
T224 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1618337817 May 30 03:33:08 PM PDT 24 May 30 03:39:01 PM PDT 24 14607901265 ps
T225 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2612086855 May 30 03:29:32 PM PDT 24 May 30 03:29:54 PM PDT 24 515318373 ps
T226 /workspace/coverage/default/22.sram_ctrl_ram_cfg.4274786733 May 30 03:29:54 PM PDT 24 May 30 03:29:55 PM PDT 24 28959777 ps
T227 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1551826438 May 30 03:31:13 PM PDT 24 May 30 03:31:59 PM PDT 24 113278431 ps
T150 /workspace/coverage/default/16.sram_ctrl_regwen.2261119830 May 30 03:28:58 PM PDT 24 May 30 03:45:59 PM PDT 24 26772451698 ps
T228 /workspace/coverage/default/3.sram_ctrl_partial_access.1390572613 May 30 03:27:17 PM PDT 24 May 30 03:28:50 PM PDT 24 362799347 ps
T229 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1186283302 May 30 03:32:17 PM PDT 24 May 30 03:32:23 PM PDT 24 181970160 ps
T230 /workspace/coverage/default/30.sram_ctrl_mem_walk.2704973856 May 30 03:31:12 PM PDT 24 May 30 03:31:19 PM PDT 24 899825639 ps
T43 /workspace/coverage/default/30.sram_ctrl_regwen.775586303 May 30 03:31:12 PM PDT 24 May 30 03:45:31 PM PDT 24 124169482818 ps
T231 /workspace/coverage/default/1.sram_ctrl_bijection.2466233754 May 30 03:27:08 PM PDT 24 May 30 03:27:24 PM PDT 24 242255792 ps
T232 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.904711355 May 30 03:33:29 PM PDT 24 May 30 03:33:37 PM PDT 24 771626715 ps
T80 /workspace/coverage/default/19.sram_ctrl_executable.2811632486 May 30 03:29:35 PM PDT 24 May 30 03:47:27 PM PDT 24 74928761263 ps
T233 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.566140506 May 30 03:32:59 PM PDT 24 May 30 03:33:48 PM PDT 24 458540835 ps
T234 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1501189960 May 30 03:31:11 PM PDT 24 May 30 03:31:13 PM PDT 24 35682952 ps
T235 /workspace/coverage/default/6.sram_ctrl_multiple_keys.1752195202 May 30 03:27:39 PM PDT 24 May 30 03:38:36 PM PDT 24 105792585473 ps
T236 /workspace/coverage/default/48.sram_ctrl_executable.4047944247 May 30 03:33:39 PM PDT 24 May 30 03:44:05 PM PDT 24 2151887622 ps
T237 /workspace/coverage/default/23.sram_ctrl_regwen.3284927930 May 30 03:30:08 PM PDT 24 May 30 03:35:21 PM PDT 24 4294932203 ps
T149 /workspace/coverage/default/36.sram_ctrl_executable.1812451288 May 30 03:31:56 PM PDT 24 May 30 03:52:06 PM PDT 24 82715093597 ps
T238 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.170696852 May 30 03:32:10 PM PDT 24 May 30 03:33:22 PM PDT 24 505086452 ps
T239 /workspace/coverage/default/29.sram_ctrl_executable.1969183359 May 30 03:31:02 PM PDT 24 May 30 03:42:00 PM PDT 24 5472555321 ps
T240 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.4100147587 May 30 03:27:05 PM PDT 24 May 30 03:27:11 PM PDT 24 191729757 ps
T241 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3457191375 May 30 03:30:40 PM PDT 24 May 30 03:34:53 PM PDT 24 19908172739 ps
T242 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3531350231 May 30 03:27:06 PM PDT 24 May 30 03:27:08 PM PDT 24 28221053 ps
T243 /workspace/coverage/default/12.sram_ctrl_ram_cfg.1065913855 May 30 03:28:29 PM PDT 24 May 30 03:28:31 PM PDT 24 84790947 ps
T244 /workspace/coverage/default/26.sram_ctrl_partial_access.619689421 May 30 03:30:32 PM PDT 24 May 30 03:30:45 PM PDT 24 1005528195 ps
T245 /workspace/coverage/default/49.sram_ctrl_bijection.40011626 May 30 03:33:51 PM PDT 24 May 30 03:34:07 PM PDT 24 230341387 ps
T246 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1771268463 May 30 03:30:12 PM PDT 24 May 30 03:31:15 PM PDT 24 469597706 ps
T247 /workspace/coverage/default/27.sram_ctrl_mem_walk.1882361784 May 30 03:30:40 PM PDT 24 May 30 03:30:51 PM PDT 24 881576704 ps
T248 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.722599994 May 30 03:27:56 PM PDT 24 May 30 03:28:00 PM PDT 24 232871144 ps
T249 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.752669633 May 30 03:31:57 PM PDT 24 May 30 03:36:06 PM PDT 24 10356031812 ps
T250 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3828252580 May 30 03:27:17 PM PDT 24 May 30 03:33:00 PM PDT 24 6687151555 ps
T251 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3579919079 May 30 03:28:31 PM PDT 24 May 30 03:28:37 PM PDT 24 189611128 ps
T252 /workspace/coverage/default/31.sram_ctrl_partial_access.2842321354 May 30 03:31:13 PM PDT 24 May 30 03:31:34 PM PDT 24 1001435524 ps
T81 /workspace/coverage/default/43.sram_ctrl_regwen.3038648547 May 30 03:33:01 PM PDT 24 May 30 03:50:31 PM PDT 24 6338582797 ps
T253 /workspace/coverage/default/9.sram_ctrl_regwen.2314099934 May 30 03:28:06 PM PDT 24 May 30 04:00:18 PM PDT 24 69784133853 ps
T82 /workspace/coverage/default/24.sram_ctrl_regwen.1710577217 May 30 03:30:11 PM PDT 24 May 30 03:39:12 PM PDT 24 8043125146 ps
T254 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.205607307 May 30 03:32:20 PM PDT 24 May 30 03:37:33 PM PDT 24 9073655877 ps
T255 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3555211574 May 30 03:33:24 PM PDT 24 May 30 03:33:32 PM PDT 24 2097884619 ps
T256 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1117857458 May 30 03:29:33 PM PDT 24 May 30 03:37:55 PM PDT 24 18614158876 ps
T257 /workspace/coverage/default/16.sram_ctrl_smoke.355697579 May 30 03:28:58 PM PDT 24 May 30 03:29:16 PM PDT 24 290767800 ps
T258 /workspace/coverage/default/22.sram_ctrl_mem_walk.2174162466 May 30 03:29:55 PM PDT 24 May 30 03:30:05 PM PDT 24 392829088 ps
T259 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4105565772 May 30 03:28:58 PM PDT 24 May 30 03:30:01 PM PDT 24 437812143 ps
T260 /workspace/coverage/default/14.sram_ctrl_max_throughput.3006160902 May 30 03:28:41 PM PDT 24 May 30 03:28:50 PM PDT 24 68187218 ps
T261 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1864477447 May 30 03:30:21 PM PDT 24 May 30 03:31:14 PM PDT 24 889529984 ps
T262 /workspace/coverage/default/14.sram_ctrl_multiple_keys.3718143992 May 30 03:28:41 PM PDT 24 May 30 03:38:16 PM PDT 24 2186094928 ps
T263 /workspace/coverage/default/5.sram_ctrl_partial_access.2573484536 May 30 03:27:39 PM PDT 24 May 30 03:27:42 PM PDT 24 85218352 ps
T264 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.709134702 May 30 03:28:04 PM PDT 24 May 30 03:35:20 PM PDT 24 28393660815 ps
T265 /workspace/coverage/default/28.sram_ctrl_partial_access.1333392822 May 30 03:30:41 PM PDT 24 May 30 03:31:08 PM PDT 24 377878632 ps
T266 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2468477771 May 30 03:27:18 PM PDT 24 May 30 03:32:40 PM PDT 24 21184873881 ps
T267 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3064845695 May 30 03:29:54 PM PDT 24 May 30 03:33:08 PM PDT 24 2078918935 ps
T268 /workspace/coverage/default/17.sram_ctrl_mem_walk.1749065582 May 30 03:29:11 PM PDT 24 May 30 03:29:24 PM PDT 24 598660073 ps
T269 /workspace/coverage/default/21.sram_ctrl_mem_walk.407763143 May 30 03:29:44 PM PDT 24 May 30 03:29:57 PM PDT 24 692345013 ps
T270 /workspace/coverage/default/26.sram_ctrl_executable.4027483099 May 30 03:30:36 PM PDT 24 May 30 03:35:03 PM PDT 24 2842483673 ps
T271 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1209286627 May 30 03:31:03 PM PDT 24 May 30 03:36:00 PM PDT 24 15857460222 ps
T272 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1841550467 May 30 03:30:50 PM PDT 24 May 30 03:30:55 PM PDT 24 376134736 ps
T273 /workspace/coverage/default/33.sram_ctrl_partial_access.951467946 May 30 03:31:33 PM PDT 24 May 30 03:31:36 PM PDT 24 61217662 ps
T142 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2404495816 May 30 03:28:30 PM PDT 24 May 30 03:28:39 PM PDT 24 2622925439 ps
T274 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4022342873 May 30 03:27:38 PM PDT 24 May 30 03:34:26 PM PDT 24 31837381905 ps
T275 /workspace/coverage/default/26.sram_ctrl_mem_walk.3086903636 May 30 03:30:33 PM PDT 24 May 30 03:30:44 PM PDT 24 462381084 ps
T276 /workspace/coverage/default/25.sram_ctrl_ram_cfg.1665136398 May 30 03:30:21 PM PDT 24 May 30 03:30:24 PM PDT 24 41680005 ps
T277 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2705225016 May 30 03:28:40 PM PDT 24 May 30 03:29:55 PM PDT 24 1618162354 ps
T278 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4193087834 May 30 03:28:29 PM PDT 24 May 30 03:33:31 PM PDT 24 49168083631 ps
T279 /workspace/coverage/default/7.sram_ctrl_multiple_keys.2321416015 May 30 03:27:39 PM PDT 24 May 30 03:48:36 PM PDT 24 5316373909 ps
T280 /workspace/coverage/default/1.sram_ctrl_lc_escalation.883537647 May 30 03:27:06 PM PDT 24 May 30 03:27:12 PM PDT 24 1417059854 ps
T281 /workspace/coverage/default/28.sram_ctrl_executable.1676675209 May 30 03:30:51 PM PDT 24 May 30 03:38:24 PM PDT 24 31421823421 ps
T282 /workspace/coverage/default/16.sram_ctrl_multiple_keys.4235849201 May 30 03:28:59 PM PDT 24 May 30 03:55:03 PM PDT 24 17791461530 ps
T156 /workspace/coverage/default/28.sram_ctrl_lc_escalation.1322599878 May 30 03:30:51 PM PDT 24 May 30 03:30:59 PM PDT 24 486016924 ps
T283 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1455617284 May 30 03:31:50 PM PDT 24 May 30 03:31:54 PM PDT 24 119899124 ps
T284 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1537760055 May 30 03:33:41 PM PDT 24 May 30 03:33:45 PM PDT 24 184401720 ps
T285 /workspace/coverage/default/9.sram_ctrl_smoke.343986783 May 30 03:28:05 PM PDT 24 May 30 03:28:23 PM PDT 24 283774375 ps
T286 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2491654344 May 30 03:28:59 PM PDT 24 May 30 03:32:43 PM PDT 24 15058421983 ps
T287 /workspace/coverage/default/21.sram_ctrl_alert_test.1677942732 May 30 03:29:56 PM PDT 24 May 30 03:29:57 PM PDT 24 36234132 ps
T288 /workspace/coverage/default/29.sram_ctrl_partial_access.4045055950 May 30 03:30:53 PM PDT 24 May 30 03:31:06 PM PDT 24 2572999133 ps
T289 /workspace/coverage/default/32.sram_ctrl_mem_walk.157681327 May 30 03:31:25 PM PDT 24 May 30 03:31:36 PM PDT 24 894537848 ps
T290 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3156534137 May 30 03:30:33 PM PDT 24 May 30 03:37:17 PM PDT 24 19419908618 ps
T291 /workspace/coverage/default/35.sram_ctrl_alert_test.412344119 May 30 03:31:57 PM PDT 24 May 30 03:31:59 PM PDT 24 15094750 ps
T292 /workspace/coverage/default/1.sram_ctrl_executable.553570168 May 30 03:27:06 PM PDT 24 May 30 03:32:52 PM PDT 24 91658804086 ps
T293 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3815005570 May 30 03:32:43 PM PDT 24 May 30 03:37:58 PM PDT 24 13423146141 ps
T155 /workspace/coverage/default/11.sram_ctrl_lc_escalation.3222234752 May 30 03:28:17 PM PDT 24 May 30 03:28:24 PM PDT 24 339204397 ps
T294 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3722616211 May 30 03:29:44 PM PDT 24 May 30 03:29:51 PM PDT 24 1069512037 ps
T295 /workspace/coverage/default/4.sram_ctrl_smoke.3535563671 May 30 03:27:29 PM PDT 24 May 30 03:27:35 PM PDT 24 750414716 ps
T296 /workspace/coverage/default/43.sram_ctrl_mem_walk.4105371543 May 30 03:32:59 PM PDT 24 May 30 03:33:06 PM PDT 24 966606550 ps
T297 /workspace/coverage/default/7.sram_ctrl_executable.1142562837 May 30 03:27:48 PM PDT 24 May 30 03:48:36 PM PDT 24 50639354321 ps
T298 /workspace/coverage/default/40.sram_ctrl_regwen.3613888187 May 30 03:32:32 PM PDT 24 May 30 03:42:25 PM PDT 24 10748277843 ps
T299 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3227026647 May 30 03:29:12 PM PDT 24 May 30 03:32:20 PM PDT 24 8116556605 ps
T300 /workspace/coverage/default/25.sram_ctrl_regwen.288606607 May 30 03:30:20 PM PDT 24 May 30 03:40:47 PM PDT 24 38567457612 ps
T301 /workspace/coverage/default/1.sram_ctrl_alert_test.3491594146 May 30 03:27:06 PM PDT 24 May 30 03:27:08 PM PDT 24 13539950 ps
T302 /workspace/coverage/default/13.sram_ctrl_regwen.2753760874 May 30 03:28:40 PM PDT 24 May 30 03:42:20 PM PDT 24 7751337445 ps
T303 /workspace/coverage/default/19.sram_ctrl_smoke.3018079871 May 30 03:29:24 PM PDT 24 May 30 03:29:44 PM PDT 24 1897616395 ps
T304 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2560607520 May 30 03:30:31 PM PDT 24 May 30 03:30:33 PM PDT 24 55297166 ps
T305 /workspace/coverage/default/25.sram_ctrl_lc_escalation.2491118857 May 30 03:30:22 PM PDT 24 May 30 03:30:31 PM PDT 24 4048909471 ps
T306 /workspace/coverage/default/30.sram_ctrl_partial_access.2739349495 May 30 03:31:03 PM PDT 24 May 30 03:31:16 PM PDT 24 647890815 ps
T307 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.231923488 May 30 03:33:11 PM PDT 24 May 30 03:33:15 PM PDT 24 84897545 ps
T308 /workspace/coverage/default/37.sram_ctrl_lc_escalation.4032098453 May 30 03:32:13 PM PDT 24 May 30 03:32:23 PM PDT 24 919986016 ps
T309 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2253712380 May 30 03:29:11 PM PDT 24 May 30 03:36:52 PM PDT 24 141307732851 ps
T310 /workspace/coverage/default/18.sram_ctrl_partial_access.3667947260 May 30 03:29:24 PM PDT 24 May 30 03:30:52 PM PDT 24 346502123 ps
T311 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.4001544503 May 30 03:30:35 PM PDT 24 May 30 03:36:22 PM PDT 24 22085147754 ps
T312 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2370573262 May 30 03:32:32 PM PDT 24 May 30 03:32:40 PM PDT 24 711935461 ps
T313 /workspace/coverage/default/27.sram_ctrl_regwen.3609439017 May 30 03:30:48 PM PDT 24 May 30 03:48:46 PM PDT 24 19673939537 ps
T314 /workspace/coverage/default/46.sram_ctrl_partial_access.3003255607 May 30 03:33:19 PM PDT 24 May 30 03:33:36 PM PDT 24 290829350 ps
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