Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	26049281	1			T1	43008		T2	43008		T3	3071
triple_byte_access	2177730	1			T9	65		T4	16		T10	803
halfword_access	3269134	1			T9	98		T4	19		T10	1277
byte_access	4366113	1			T9	135		T4	26		T10	1670
zero_access	1101876	1			T9	30		T4	5		T10	439

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18443384

1

T1

21504

T2

21504

T3

1024

auto[1]

18520750

1

T1

21504

T2

21504

T3

2047

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	12988828	1			T1	21504		T2	21504		T3	1024
auto[0]	triple_byte_access	1085189	1			T9	30		T4	12		T10	408
auto[0]	halfword_access	1630852	1			T9	59		T4	12		T10	636
auto[0]	byte_access	2182818	1			T9	75		T4	13		T10	821
auto[0]	zero_access	555697	1			T9	16		T4	5		T10	224
auto[1]	word_access	13060453	1			T1	21504		T2	21504		T3	2047
auto[1]	triple_byte_access	1092541	1			T9	35		T4	4		T10	395
auto[1]	halfword_access	1638282	1			T9	39		T4	7		T10	641
auto[1]	byte_access	2183295	1			T9	60		T4	13		T10	849
auto[1]	zero_access	546179	1			T9	14		T10	215		T5	82