Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	86595832	1			T1	9804		T2	17300		T3	102400
instr_valid_dis	72112294	1			T1	9804		T2	17300		T3	102400
instr_en	10397859	1			T14	684		T24	33906		T45	45950

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	4304952	1			T24	72952		T25	180740		T26	17336
sram_ifetch_valid_disable	71183844	1			T1	9804		T2	17300		T3	102400
sram_ifetch_enable	11107036	1			T14	684		T24	338636		T25	92

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	86595832	1			T1	9804		T2	17300		T3	102400
hw_debug_en_valid_off	70440064	1			T1	9804		T2	17300		T3	102400
hw_debug_en_on	10115786	1			T14	684		T24	337196		T25	142346

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	71183844	1			T1	9804		T2	17300		T3	102400
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	65093516	1			T1	9804		T2	17300		T3	102400
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4383861	1			T24	86		T45	16216		T118	97776
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	1254972	1			T25	98292		T26	10718		T45	15418
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	415540	1			T45	15418		T148	6870		T156	29082
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	554928	1			T118	11998		T120	39860		T147	692
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	1806800	1			T24	16256		T25	70144		T118	594
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	680694	1			T24	16256		T120	19574		T147	222
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	733538	1			T118	594		T69	18940		T146	12724
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4168024	1			T24	78282		T25	72202		T26	39100
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1525490	1			T24	78282		T25	568		T45	12696
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1801386	1			T118	43778		T120	47514		T148	37674

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4433552	1			T14	684		T24	33820		T45	29734
lc_exec_en	4140962	1			T14	684		T24	242658		T66	37884
valid_exec_dis	69937334	1			T1	9804		T2	17300		T3	102400
invalid_exec_dis	15411988	1			T14	684		T24	411588		T25	180832