Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.22 99.18 95.41 100.00 100.00 96.12 99.56 97.26


Total tests in report: 889
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
80.85 80.85 95.71 95.71 80.22 80.22 92.79 92.79 61.90 61.90 85.65 85.65 94.68 94.68 55.03 55.03 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1584227346
89.70 8.85 98.51 2.81 85.13 4.92 96.32 3.54 100.00 38.10 92.13 6.48 95.13 0.44 60.69 5.67 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2517396739
92.60 2.90 98.76 0.25 87.77 2.64 97.68 1.36 100.00 0.00 93.75 1.62 95.27 0.15 74.95 14.26 /workspace/coverage/default/36.sram_ctrl_regwen.3239253313
93.68 1.08 98.76 0.00 88.25 0.48 97.68 0.00 100.00 0.00 94.44 0.69 95.27 0.00 81.35 6.40 /workspace/coverage/default/20.sram_ctrl_executable.4284548850
94.70 1.02 98.93 0.17 88.85 0.60 97.89 0.21 100.00 0.00 95.14 0.69 95.27 0.00 86.84 5.48 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.134016501
95.28 0.58 99.09 0.17 90.65 1.80 98.32 0.43 100.00 0.00 95.83 0.69 95.86 0.59 87.20 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.665329350
95.79 0.51 99.09 0.00 90.65 0.00 98.64 0.32 100.00 0.00 95.83 0.00 96.01 0.15 90.31 3.11 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3761699298
96.19 0.39 99.09 0.00 91.25 0.60 98.71 0.07 100.00 0.00 96.30 0.46 97.64 1.62 90.31 0.00 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1708044543
96.50 0.31 99.09 0.00 91.25 0.00 98.71 0.00 100.00 0.00 96.30 0.00 97.64 0.00 92.50 2.19 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.593262690
96.75 0.26 99.09 0.00 91.25 0.00 98.71 0.00 100.00 0.00 96.30 0.00 97.78 0.15 94.15 1.65 /workspace/coverage/default/10.sram_ctrl_executable.3358816235
96.98 0.22 99.09 0.00 91.25 0.00 98.79 0.07 100.00 0.00 96.30 0.00 99.26 1.48 94.15 0.00 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4285452774
97.17 0.19 99.09 0.00 91.61 0.36 99.21 0.43 100.00 0.00 96.30 0.00 99.26 0.00 94.70 0.55 /workspace/coverage/default/13.sram_ctrl_alert_test.693557174
97.28 0.11 99.17 0.08 91.61 0.00 99.93 0.71 100.00 0.00 96.30 0.00 99.26 0.00 94.70 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.2050727559
97.39 0.10 99.17 0.00 91.61 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.26 0.00 95.43 0.73 /workspace/coverage/default/24.sram_ctrl_executable.3023123644
97.47 0.09 99.17 0.00 91.85 0.24 99.93 0.00 100.00 0.00 96.30 0.00 99.26 0.00 95.80 0.37 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2678332314
97.55 0.08 99.17 0.00 91.85 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.26 0.00 96.34 0.55 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4240409121
97.60 0.05 99.17 0.00 91.85 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.26 0.00 96.71 0.37 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.197542547
97.64 0.04 99.17 0.00 91.85 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.30 96.71 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.372617037
97.68 0.03 99.17 0.00 92.09 0.24 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.00 96.71 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3857623661
97.71 0.03 99.17 0.00 92.09 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.00 96.89 0.18 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.444663941
97.73 0.03 99.17 0.00 92.09 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2132907072
97.76 0.03 99.17 0.00 92.09 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.00 97.26 0.18 /workspace/coverage/default/0.sram_ctrl_executable.4087240586
97.77 0.01 99.17 0.00 92.09 0.00 100.00 0.07 100.00 0.00 96.30 0.00 99.56 0.00 97.26 0.00 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3253942136

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3992437679
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1525349268
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3496889702
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1797807874
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1568131634
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4115438103
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.479410630
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1330598363
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2699537891
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3231010780
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2064879024
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3533409912
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3017714511
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4028044545
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.727150870
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3563761876
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2073384841
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3240002131
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3255799890
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1177786716
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1008257816
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3718023328
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2759308331
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1234095924
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2148247144
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2975554135
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2083664561
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1723112817
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3899184149
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1600276152
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1912079847
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1548878979
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3815422756
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3935308079
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2264489182
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1702008714
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1633089523
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.989459079
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.490005329
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.789547222
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3010722487
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3613414772
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2086808650
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1673526784
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3910206173
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.11638073
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2783505623
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1317156522
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3128638847
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3899576701
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.501923925
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1228992477
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2268789854
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2801922139
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3583330635
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3817801881
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.668137238
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1425403435
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3157590533
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.575880504
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1272027020
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.908720063
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2679638978
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2973205318
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4117596922
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3364554980
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2424473805
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1105077469
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2895405762
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3173035550
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3053517370
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1443301483
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1400495680
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1116532537
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.553793648
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3339206936
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3156147969
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.451858146
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2908333221
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3862036972
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.859333219
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3775895244
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2582379198
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2044980201
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4235249325
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1088066118
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3082856222
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.828149315
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1620344840
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.453698607
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3912232977
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.142962466
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1204409508
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.507042271
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3157166055
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3925580640
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1890111112
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1855628124
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4024041967
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3461019444
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.313913241
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.606808235
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1030317369
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2275610324
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2517684008
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.228186452
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3867954720
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1820751794
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2126155968
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3373401526
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1750025166
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.959050344
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2107259181
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2597917471
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3016423603
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4242903319
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4093336202
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2579207502
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.723749468
/workspace/coverage/default/0.sram_ctrl_alert_test.1465603546
/workspace/coverage/default/0.sram_ctrl_bijection.3336773507
/workspace/coverage/default/0.sram_ctrl_max_throughput.1135309463
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3587416227
/workspace/coverage/default/0.sram_ctrl_mem_walk.3517490562
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2467721662
/workspace/coverage/default/0.sram_ctrl_partial_access.964035288
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2266267839
/workspace/coverage/default/0.sram_ctrl_ram_cfg.4134591501
/workspace/coverage/default/0.sram_ctrl_regwen.1199083927
/workspace/coverage/default/0.sram_ctrl_smoke.1591524172
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1397269
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2803152345
/workspace/coverage/default/1.sram_ctrl_alert_test.3863673198
/workspace/coverage/default/1.sram_ctrl_bijection.917435717
/workspace/coverage/default/1.sram_ctrl_executable.4175832252
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3993080310
/workspace/coverage/default/1.sram_ctrl_max_throughput.527617622
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1689259529
/workspace/coverage/default/1.sram_ctrl_mem_walk.1632871145
/workspace/coverage/default/1.sram_ctrl_partial_access.659244943
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3582919788
/workspace/coverage/default/1.sram_ctrl_regwen.879712429
/workspace/coverage/default/1.sram_ctrl_sec_cm.2500561932
/workspace/coverage/default/1.sram_ctrl_smoke.1696063626
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1109172812
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3083750885
/workspace/coverage/default/10.sram_ctrl_alert_test.3090719826
/workspace/coverage/default/10.sram_ctrl_bijection.3837535930
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1940117661
/workspace/coverage/default/10.sram_ctrl_max_throughput.1291781055
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4105151009
/workspace/coverage/default/10.sram_ctrl_mem_walk.3572180786
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4153309648
/workspace/coverage/default/10.sram_ctrl_partial_access.1573295720
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1466033012
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1459601454
/workspace/coverage/default/10.sram_ctrl_regwen.1904127433
/workspace/coverage/default/10.sram_ctrl_smoke.1795768051
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1419183119
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3962774026
/workspace/coverage/default/11.sram_ctrl_alert_test.1308880942
/workspace/coverage/default/11.sram_ctrl_bijection.3451199114
/workspace/coverage/default/11.sram_ctrl_executable.1426868123
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3007659332
/workspace/coverage/default/11.sram_ctrl_max_throughput.597039318
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2632101545
/workspace/coverage/default/11.sram_ctrl_mem_walk.1934758021
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4212450121
/workspace/coverage/default/11.sram_ctrl_partial_access.1016048990
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1458087296
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2503600370
/workspace/coverage/default/11.sram_ctrl_regwen.3622443898
/workspace/coverage/default/11.sram_ctrl_smoke.3428041946
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.450363924
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3237134441
/workspace/coverage/default/12.sram_ctrl_alert_test.3962502045
/workspace/coverage/default/12.sram_ctrl_bijection.153919916
/workspace/coverage/default/12.sram_ctrl_executable.2014370128
/workspace/coverage/default/12.sram_ctrl_max_throughput.1460855213
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2877940624
/workspace/coverage/default/12.sram_ctrl_mem_walk.481875647
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2569290770
/workspace/coverage/default/12.sram_ctrl_partial_access.1197100342
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3593397032
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3558396338
/workspace/coverage/default/12.sram_ctrl_regwen.3662294180
/workspace/coverage/default/12.sram_ctrl_smoke.354805168
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2980038283
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2282465038
/workspace/coverage/default/13.sram_ctrl_bijection.4113609891
/workspace/coverage/default/13.sram_ctrl_executable.2325956570
/workspace/coverage/default/13.sram_ctrl_lc_escalation.65498047
/workspace/coverage/default/13.sram_ctrl_max_throughput.323641754
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.4231749791
/workspace/coverage/default/13.sram_ctrl_mem_walk.1447259687
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2346768518
/workspace/coverage/default/13.sram_ctrl_partial_access.1409381356
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.4136776234
/workspace/coverage/default/13.sram_ctrl_ram_cfg.874619245
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/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.90400056
/workspace/coverage/default/6.sram_ctrl_alert_test.22219616
/workspace/coverage/default/6.sram_ctrl_bijection.2162915976
/workspace/coverage/default/6.sram_ctrl_executable.2689887952
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2349763369
/workspace/coverage/default/6.sram_ctrl_max_throughput.2394959143
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2388339968
/workspace/coverage/default/6.sram_ctrl_mem_walk.2261389941
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2369087455
/workspace/coverage/default/6.sram_ctrl_partial_access.1067152302
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.570924051
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1005890472
/workspace/coverage/default/6.sram_ctrl_regwen.3893795602
/workspace/coverage/default/6.sram_ctrl_smoke.2086645386
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2265849160
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1774174559
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2239661393
/workspace/coverage/default/7.sram_ctrl_alert_test.2852341670
/workspace/coverage/default/7.sram_ctrl_bijection.2668939269
/workspace/coverage/default/7.sram_ctrl_executable.2831638640
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1704165521
/workspace/coverage/default/7.sram_ctrl_max_throughput.3555816436
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2862774336
/workspace/coverage/default/7.sram_ctrl_mem_walk.1061188367
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2566046436
/workspace/coverage/default/7.sram_ctrl_partial_access.4230144162
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3745164665
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1083371463
/workspace/coverage/default/7.sram_ctrl_regwen.1292159700
/workspace/coverage/default/7.sram_ctrl_smoke.866054991
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1464229920
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2771655574
/workspace/coverage/default/8.sram_ctrl_alert_test.3438426466
/workspace/coverage/default/8.sram_ctrl_bijection.1071773551
/workspace/coverage/default/8.sram_ctrl_executable.2024671557
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2219688076
/workspace/coverage/default/8.sram_ctrl_max_throughput.489999622
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1366903803
/workspace/coverage/default/8.sram_ctrl_mem_walk.2913584914
/workspace/coverage/default/8.sram_ctrl_multiple_keys.487336198
/workspace/coverage/default/8.sram_ctrl_partial_access.1423635206
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1293427023
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1925284055
/workspace/coverage/default/8.sram_ctrl_regwen.1760209858
/workspace/coverage/default/8.sram_ctrl_smoke.2365579741
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.492006396
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.733934150
/workspace/coverage/default/9.sram_ctrl_alert_test.1436517227
/workspace/coverage/default/9.sram_ctrl_bijection.723869013
/workspace/coverage/default/9.sram_ctrl_executable.3785203967
/workspace/coverage/default/9.sram_ctrl_lc_escalation.442807728
/workspace/coverage/default/9.sram_ctrl_max_throughput.3284198892
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4285369766
/workspace/coverage/default/9.sram_ctrl_mem_walk.3513248519
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3346101831
/workspace/coverage/default/9.sram_ctrl_partial_access.3678426966
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2951317486
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3365637138
/workspace/coverage/default/9.sram_ctrl_regwen.3154348413
/workspace/coverage/default/9.sram_ctrl_smoke.2987166407
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2161818856
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3379326463



Total test records in report: 889
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/26.sram_ctrl_max_throughput.2950535554 Jun 02 01:29:50 PM PDT 24 Jun 02 01:30:14 PM PDT 24 162495596 ps
T2 /workspace/coverage/default/29.sram_ctrl_max_throughput.4107966101 Jun 02 01:30:16 PM PDT 24 Jun 02 01:31:50 PM PDT 24 124987267 ps
T3 /workspace/coverage/default/34.sram_ctrl_bijection.3458505449 Jun 02 01:30:48 PM PDT 24 Jun 02 01:32:28 PM PDT 24 19583814551 ps
T4 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1188056818 Jun 02 01:28:33 PM PDT 24 Jun 02 01:31:01 PM PDT 24 542884794 ps
T5 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1708044543 Jun 02 01:28:40 PM PDT 24 Jun 02 01:28:46 PM PDT 24 318667267 ps
T9 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1584227346 Jun 02 01:29:01 PM PDT 24 Jun 02 01:29:34 PM PDT 24 691527890 ps
T10 /workspace/coverage/default/27.sram_ctrl_partial_access.2540560153 Jun 02 01:29:53 PM PDT 24 Jun 02 01:30:12 PM PDT 24 1060669487 ps
T11 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3253942136 Jun 02 01:28:38 PM PDT 24 Jun 02 01:32:42 PM PDT 24 13963520313 ps
T12 /workspace/coverage/default/49.sram_ctrl_mem_walk.1914956034 Jun 02 01:32:57 PM PDT 24 Jun 02 01:33:09 PM PDT 24 11383226210 ps
T13 /workspace/coverage/default/40.sram_ctrl_max_throughput.1384797901 Jun 02 01:31:35 PM PDT 24 Jun 02 01:32:48 PM PDT 24 203371716 ps
T6 /workspace/coverage/default/20.sram_ctrl_lc_escalation.4018069427 Jun 02 01:29:16 PM PDT 24 Jun 02 01:29:24 PM PDT 24 2741987481 ps
T15 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4294026755 Jun 02 01:28:05 PM PDT 24 Jun 02 01:31:29 PM PDT 24 4691855041 ps
T17 /workspace/coverage/default/45.sram_ctrl_alert_test.2124356836 Jun 02 01:32:24 PM PDT 24 Jun 02 01:32:25 PM PDT 24 18783838 ps
T16 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2377341604 Jun 02 01:31:56 PM PDT 24 Jun 02 01:34:33 PM PDT 24 2096966003 ps
T48 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1488075967 Jun 02 01:31:14 PM PDT 24 Jun 02 01:35:10 PM PDT 24 3472292905 ps
T49 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.90400056 Jun 02 01:28:04 PM PDT 24 Jun 02 01:28:41 PM PDT 24 109014145 ps
T68 /workspace/coverage/default/47.sram_ctrl_max_throughput.2550600976 Jun 02 01:32:36 PM PDT 24 Jun 02 01:34:04 PM PDT 24 423763274 ps
T46 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.527055011 Jun 02 01:31:08 PM PDT 24 Jun 02 01:31:14 PM PDT 24 741533251 ps
T50 /workspace/coverage/default/5.sram_ctrl_multiple_keys.3396176800 Jun 02 01:27:57 PM PDT 24 Jun 02 01:46:51 PM PDT 24 15744706901 ps
T7 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2517396739 Jun 02 01:28:28 PM PDT 24 Jun 02 01:28:33 PM PDT 24 956156348 ps
T14 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1697076241 Jun 02 01:29:51 PM PDT 24 Jun 02 01:29:59 PM PDT 24 245868294 ps
T116 /workspace/coverage/default/21.sram_ctrl_bijection.2144401811 Jun 02 01:29:15 PM PDT 24 Jun 02 01:29:56 PM PDT 24 4910533512 ps
T117 /workspace/coverage/default/5.sram_ctrl_mem_walk.3265188592 Jun 02 01:28:04 PM PDT 24 Jun 02 01:28:09 PM PDT 24 75038293 ps
T51 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2388339968 Jun 02 01:28:03 PM PDT 24 Jun 02 01:28:07 PM PDT 24 372083475 ps
T123 /workspace/coverage/default/9.sram_ctrl_max_throughput.3284198892 Jun 02 01:28:20 PM PDT 24 Jun 02 01:29:08 PM PDT 24 203485387 ps
T18 /workspace/coverage/default/30.sram_ctrl_alert_test.3090787585 Jun 02 01:30:23 PM PDT 24 Jun 02 01:30:24 PM PDT 24 12856052 ps
T24 /workspace/coverage/default/42.sram_ctrl_regwen.2140840104 Jun 02 01:31:55 PM PDT 24 Jun 02 01:49:44 PM PDT 24 4965399290 ps
T8 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2678332314 Jun 02 01:27:46 PM PDT 24 Jun 02 01:27:52 PM PDT 24 1305482315 ps
T124 /workspace/coverage/default/29.sram_ctrl_bijection.146600589 Jun 02 01:30:17 PM PDT 24 Jun 02 01:31:26 PM PDT 24 26615681112 ps
T125 /workspace/coverage/default/47.sram_ctrl_bijection.2022146865 Jun 02 01:32:29 PM PDT 24 Jun 02 01:33:38 PM PDT 24 1153486774 ps
T163 /workspace/coverage/default/43.sram_ctrl_max_throughput.554831377 Jun 02 01:32:01 PM PDT 24 Jun 02 01:33:40 PM PDT 24 549773576 ps
T164 /workspace/coverage/default/14.sram_ctrl_smoke.1809965289 Jun 02 01:28:38 PM PDT 24 Jun 02 01:28:45 PM PDT 24 180316076 ps
T25 /workspace/coverage/default/36.sram_ctrl_regwen.3239253313 Jun 02 01:31:07 PM PDT 24 Jun 02 01:46:36 PM PDT 24 28316473722 ps
T47 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2486496864 Jun 02 01:30:47 PM PDT 24 Jun 02 01:30:51 PM PDT 24 90810043 ps
T29 /workspace/coverage/default/29.sram_ctrl_lc_escalation.2568224432 Jun 02 01:30:15 PM PDT 24 Jun 02 01:30:18 PM PDT 24 255499504 ps
T31 /workspace/coverage/default/12.sram_ctrl_ram_cfg.3558396338 Jun 02 01:28:28 PM PDT 24 Jun 02 01:28:29 PM PDT 24 83901660 ps
T32 /workspace/coverage/default/1.sram_ctrl_ram_cfg.2050727559 Jun 02 01:27:53 PM PDT 24 Jun 02 01:27:55 PM PDT 24 28667839 ps
T113 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3287112047 Jun 02 01:27:59 PM PDT 24 Jun 02 01:34:06 PM PDT 24 5182714339 ps
T60 /workspace/coverage/default/22.sram_ctrl_lc_escalation.1335670267 Jun 02 01:29:21 PM PDT 24 Jun 02 01:29:26 PM PDT 24 300978533 ps
T159 /workspace/coverage/default/40.sram_ctrl_bijection.3089039904 Jun 02 01:31:33 PM PDT 24 Jun 02 01:32:26 PM PDT 24 927558183 ps
T157 /workspace/coverage/default/34.sram_ctrl_multiple_keys.2193876 Jun 02 01:30:47 PM PDT 24 Jun 02 01:46:55 PM PDT 24 41011483893 ps
T26 /workspace/coverage/default/33.sram_ctrl_regwen.2840353780 Jun 02 01:30:48 PM PDT 24 Jun 02 01:43:14 PM PDT 24 36971379204 ps
T45 /workspace/coverage/default/47.sram_ctrl_executable.2757595050 Jun 02 01:32:35 PM PDT 24 Jun 02 01:37:16 PM PDT 24 3771487362 ps
T114 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3761699298 Jun 02 01:32:11 PM PDT 24 Jun 02 01:37:23 PM PDT 24 14845000836 ps
T33 /workspace/coverage/default/39.sram_ctrl_ram_cfg.994413748 Jun 02 01:31:39 PM PDT 24 Jun 02 01:31:40 PM PDT 24 88902043 ps
T165 /workspace/coverage/default/20.sram_ctrl_smoke.409160837 Jun 02 01:29:10 PM PDT 24 Jun 02 01:29:13 PM PDT 24 64072216 ps
T118 /workspace/coverage/default/2.sram_ctrl_executable.4073463948 Jun 02 01:27:50 PM PDT 24 Jun 02 01:37:26 PM PDT 24 6526836955 ps
T20 /workspace/coverage/default/27.sram_ctrl_alert_test.2363344121 Jun 02 01:30:01 PM PDT 24 Jun 02 01:30:03 PM PDT 24 34467682 ps
T66 /workspace/coverage/default/16.sram_ctrl_regwen.2491752412 Jun 02 01:28:48 PM PDT 24 Jun 02 01:36:50 PM PDT 24 3204708234 ps
T69 /workspace/coverage/default/10.sram_ctrl_executable.3358816235 Jun 02 01:28:17 PM PDT 24 Jun 02 01:45:02 PM PDT 24 20502494278 ps
T70 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.733934150 Jun 02 01:28:13 PM PDT 24 Jun 02 01:30:41 PM PDT 24 301024559 ps
T71 /workspace/coverage/default/2.sram_ctrl_partial_access.2306747374 Jun 02 01:27:50 PM PDT 24 Jun 02 01:28:10 PM PDT 24 1015382900 ps
T67 /workspace/coverage/default/19.sram_ctrl_lc_escalation.2530743086 Jun 02 01:29:09 PM PDT 24 Jun 02 01:29:11 PM PDT 24 189370615 ps
T72 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4240409121 Jun 02 01:29:33 PM PDT 24 Jun 02 01:36:32 PM PDT 24 16135117564 ps
T73 /workspace/coverage/default/31.sram_ctrl_bijection.1649731596 Jun 02 01:30:34 PM PDT 24 Jun 02 01:31:24 PM PDT 24 754643034 ps
T74 /workspace/coverage/default/1.sram_ctrl_bijection.917435717 Jun 02 01:27:53 PM PDT 24 Jun 02 01:29:07 PM PDT 24 7243047737 ps
T75 /workspace/coverage/default/26.sram_ctrl_partial_access.903519546 Jun 02 01:29:47 PM PDT 24 Jun 02 01:32:09 PM PDT 24 4555457512 ps
T76 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1109172812 Jun 02 01:27:51 PM PDT 24 Jun 02 01:33:26 PM PDT 24 55365561041 ps
T77 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2265849160 Jun 02 01:28:03 PM PDT 24 Jun 02 01:32:29 PM PDT 24 3586834497 ps
T27 /workspace/coverage/default/24.sram_ctrl_lc_escalation.556310186 Jun 02 01:29:34 PM PDT 24 Jun 02 01:29:41 PM PDT 24 591817009 ps
T166 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2835632561 Jun 02 01:31:56 PM PDT 24 Jun 02 01:31:57 PM PDT 24 29665820 ps
T167 /workspace/coverage/default/31.sram_ctrl_mem_walk.2929133451 Jun 02 01:30:40 PM PDT 24 Jun 02 01:30:49 PM PDT 24 1285777052 ps
T168 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.494130471 Jun 02 01:30:42 PM PDT 24 Jun 02 01:31:49 PM PDT 24 1063122979 ps
T169 /workspace/coverage/default/35.sram_ctrl_ram_cfg.123465204 Jun 02 01:30:59 PM PDT 24 Jun 02 01:31:00 PM PDT 24 29326440 ps
T162 /workspace/coverage/default/33.sram_ctrl_multiple_keys.3007658295 Jun 02 01:30:40 PM PDT 24 Jun 02 01:31:12 PM PDT 24 3785770128 ps
T170 /workspace/coverage/default/10.sram_ctrl_bijection.3837535930 Jun 02 01:28:17 PM PDT 24 Jun 02 01:28:57 PM PDT 24 3221918728 ps
T171 /workspace/coverage/default/46.sram_ctrl_mem_walk.1099844363 Jun 02 01:32:29 PM PDT 24 Jun 02 01:32:35 PM PDT 24 960948045 ps
T19 /workspace/coverage/default/13.sram_ctrl_alert_test.693557174 Jun 02 01:28:39 PM PDT 24 Jun 02 01:28:40 PM PDT 24 15954746 ps
T95 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4285369766 Jun 02 01:28:18 PM PDT 24 Jun 02 01:28:22 PM PDT 24 106197924 ps
T119 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2258935670 Jun 02 01:29:32 PM PDT 24 Jun 02 01:29:40 PM PDT 24 2789420108 ps
T146 /workspace/coverage/default/7.sram_ctrl_regwen.1292159700 Jun 02 01:28:12 PM PDT 24 Jun 02 01:40:37 PM PDT 24 24087890433 ps
T115 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3355328080 Jun 02 01:27:56 PM PDT 24 Jun 02 01:31:19 PM PDT 24 3441133493 ps
T120 /workspace/coverage/default/24.sram_ctrl_executable.3023123644 Jun 02 01:29:32 PM PDT 24 Jun 02 01:46:35 PM PDT 24 20132969193 ps
T172 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.766127226 Jun 02 01:29:22 PM PDT 24 Jun 02 01:30:09 PM PDT 24 393526837 ps
T147 /workspace/coverage/default/16.sram_ctrl_executable.2594640289 Jun 02 01:28:47 PM PDT 24 Jun 02 01:47:03 PM PDT 24 14165454876 ps
T173 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1005362696 Jun 02 01:30:59 PM PDT 24 Jun 02 01:31:16 PM PDT 24 90572567 ps
T174 /workspace/coverage/default/19.sram_ctrl_mem_walk.4234826689 Jun 02 01:29:08 PM PDT 24 Jun 02 01:29:19 PM PDT 24 443145720 ps
T175 /workspace/coverage/default/38.sram_ctrl_bijection.4041143342 Jun 02 01:31:26 PM PDT 24 Jun 02 01:31:51 PM PDT 24 1154947576 ps
T160 /workspace/coverage/default/1.sram_ctrl_lc_escalation.3993080310 Jun 02 01:27:53 PM PDT 24 Jun 02 01:27:59 PM PDT 24 3847839835 ps
T176 /workspace/coverage/default/38.sram_ctrl_alert_test.1294527242 Jun 02 01:31:28 PM PDT 24 Jun 02 01:31:29 PM PDT 24 17244053 ps
T30 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.916817235 Jun 02 01:30:38 PM PDT 24 Jun 02 01:30:46 PM PDT 24 100473840 ps
T177 /workspace/coverage/default/7.sram_ctrl_mem_walk.1061188367 Jun 02 01:28:13 PM PDT 24 Jun 02 01:28:22 PM PDT 24 261327810 ps
T28 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2219688076 Jun 02 01:28:10 PM PDT 24 Jun 02 01:28:19 PM PDT 24 868273996 ps
T178 /workspace/coverage/default/11.sram_ctrl_smoke.3428041946 Jun 02 01:28:22 PM PDT 24 Jun 02 01:28:37 PM PDT 24 789203219 ps
T179 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3582919788 Jun 02 01:27:49 PM PDT 24 Jun 02 01:34:51 PM PDT 24 31106907906 ps
T180 /workspace/coverage/default/15.sram_ctrl_mem_walk.1144906324 Jun 02 01:28:42 PM PDT 24 Jun 02 01:28:49 PM PDT 24 463269283 ps
T181 /workspace/coverage/default/3.sram_ctrl_bijection.1159613315 Jun 02 01:27:56 PM PDT 24 Jun 02 01:29:08 PM PDT 24 3134222297 ps
T161 /workspace/coverage/default/7.sram_ctrl_lc_escalation.1704165521 Jun 02 01:28:04 PM PDT 24 Jun 02 01:28:13 PM PDT 24 2588915002 ps
T182 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2400493937 Jun 02 01:27:56 PM PDT 24 Jun 02 01:27:58 PM PDT 24 41751689 ps
T96 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4105151009 Jun 02 01:28:17 PM PDT 24 Jun 02 01:28:20 PM PDT 24 211286908 ps
T183 /workspace/coverage/default/6.sram_ctrl_smoke.2086645386 Jun 02 01:28:05 PM PDT 24 Jun 02 01:28:32 PM PDT 24 736066130 ps
T158 /workspace/coverage/default/38.sram_ctrl_multiple_keys.601441761 Jun 02 01:31:32 PM PDT 24 Jun 02 01:35:28 PM PDT 24 3045056915 ps
T148 /workspace/coverage/default/20.sram_ctrl_executable.4284548850 Jun 02 01:29:15 PM PDT 24 Jun 02 01:40:36 PM PDT 24 12712289438 ps
T184 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4030191886 Jun 02 01:28:48 PM PDT 24 Jun 02 01:33:02 PM PDT 24 6573767924 ps
T185 /workspace/coverage/default/24.sram_ctrl_alert_test.1051962348 Jun 02 01:29:40 PM PDT 24 Jun 02 01:29:41 PM PDT 24 90969053 ps
T156 /workspace/coverage/default/15.sram_ctrl_regwen.3877694718 Jun 02 01:28:42 PM PDT 24 Jun 02 01:38:36 PM PDT 24 5867772200 ps
T186 /workspace/coverage/default/37.sram_ctrl_ram_cfg.3254387005 Jun 02 01:31:21 PM PDT 24 Jun 02 01:31:22 PM PDT 24 68094140 ps
T187 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.368388802 Jun 02 01:32:23 PM PDT 24 Jun 02 01:36:50 PM PDT 24 7275572195 ps
T188 /workspace/coverage/default/4.sram_ctrl_alert_test.1419868828 Jun 02 01:28:01 PM PDT 24 Jun 02 01:28:02 PM PDT 24 11914492 ps
T52 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2188597363 Jun 02 01:27:59 PM PDT 24 Jun 02 01:29:21 PM PDT 24 1045267172 ps
T189 /workspace/coverage/default/10.sram_ctrl_smoke.1795768051 Jun 02 01:28:22 PM PDT 24 Jun 02 01:28:50 PM PDT 24 310099386 ps
T190 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2069331053 Jun 02 01:31:57 PM PDT 24 Jun 02 01:36:02 PM PDT 24 3920742719 ps
T191 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.432201563 Jun 02 01:29:15 PM PDT 24 Jun 02 01:34:25 PM PDT 24 11807788261 ps
T192 /workspace/coverage/default/23.sram_ctrl_alert_test.3211475753 Jun 02 01:29:34 PM PDT 24 Jun 02 01:29:35 PM PDT 24 42722080 ps
T193 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3946723884 Jun 02 01:31:07 PM PDT 24 Jun 02 01:32:00 PM PDT 24 115771304 ps
T194 /workspace/coverage/default/24.sram_ctrl_regwen.3255369159 Jun 02 01:29:36 PM PDT 24 Jun 02 01:31:28 PM PDT 24 7510332454 ps
T195 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.151428108 Jun 02 01:29:12 PM PDT 24 Jun 02 01:30:00 PM PDT 24 440356404 ps
T53 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1751456702 Jun 02 01:28:57 PM PDT 24 Jun 02 01:29:06 PM PDT 24 276938977 ps
T154 /workspace/coverage/default/38.sram_ctrl_partial_access.2403907109 Jun 02 01:31:24 PM PDT 24 Jun 02 01:31:46 PM PDT 24 2554947891 ps
T152 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2323094994 Jun 02 01:29:07 PM PDT 24 Jun 02 01:50:55 PM PDT 24 43342681579 ps
T196 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3866657589 Jun 02 01:30:23 PM PDT 24 Jun 02 01:30:29 PM PDT 24 1054829698 ps
T197 /workspace/coverage/default/15.sram_ctrl_executable.1164238738 Jun 02 01:28:42 PM PDT 24 Jun 02 01:28:48 PM PDT 24 308803136 ps
T155 /workspace/coverage/default/40.sram_ctrl_lc_escalation.1075451938 Jun 02 01:31:37 PM PDT 24 Jun 02 01:31:45 PM PDT 24 801557936 ps
T198 /workspace/coverage/default/36.sram_ctrl_alert_test.2500208131 Jun 02 01:31:17 PM PDT 24 Jun 02 01:31:18 PM PDT 24 47440936 ps
T199 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3379326463 Jun 02 01:28:22 PM PDT 24 Jun 02 01:28:25 PM PDT 24 86507959 ps
T97 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2877940624 Jun 02 01:28:28 PM PDT 24 Jun 02 01:28:33 PM PDT 24 247668974 ps
T200 /workspace/coverage/default/30.sram_ctrl_smoke.602692827 Jun 02 01:30:16 PM PDT 24 Jun 02 01:30:43 PM PDT 24 696774279 ps
T98 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2063379097 Jun 02 01:28:00 PM PDT 24 Jun 02 01:28:03 PM PDT 24 88347924 ps
T201 /workspace/coverage/default/49.sram_ctrl_max_throughput.723666358 Jun 02 01:32:51 PM PDT 24 Jun 02 01:33:26 PM PDT 24 338479855 ps
T61 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1626010712 Jun 02 01:32:56 PM PDT 24 Jun 02 01:33:01 PM PDT 24 159512249 ps
T202 /workspace/coverage/default/3.sram_ctrl_alert_test.173101375 Jun 02 01:27:59 PM PDT 24 Jun 02 01:28:00 PM PDT 24 15672875 ps
T203 /workspace/coverage/default/45.sram_ctrl_bijection.425762461 Jun 02 01:32:14 PM PDT 24 Jun 02 01:33:07 PM PDT 24 2027944313 ps
T204 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.779949505 Jun 02 01:28:39 PM PDT 24 Jun 02 01:30:19 PM PDT 24 148297712 ps
T205 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2321877542 Jun 02 01:27:58 PM PDT 24 Jun 02 01:31:52 PM PDT 24 36233565270 ps
T149 /workspace/coverage/default/4.sram_ctrl_executable.1907344734 Jun 02 01:27:58 PM PDT 24 Jun 02 01:42:27 PM PDT 24 11388640842 ps
T206 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.814155513 Jun 02 01:29:36 PM PDT 24 Jun 02 01:29:38 PM PDT 24 529131354 ps
T207 /workspace/coverage/default/42.sram_ctrl_alert_test.3283398481 Jun 02 01:31:56 PM PDT 24 Jun 02 01:31:57 PM PDT 24 12141378 ps
T208 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3668574316 Jun 02 01:29:04 PM PDT 24 Jun 02 01:29:05 PM PDT 24 86592868 ps
T209 /workspace/coverage/default/5.sram_ctrl_ram_cfg.4001759585 Jun 02 01:28:05 PM PDT 24 Jun 02 01:28:06 PM PDT 24 25856915 ps
T210 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2693106080 Jun 02 01:31:30 PM PDT 24 Jun 02 01:33:12 PM PDT 24 539452003 ps
T211 /workspace/coverage/default/21.sram_ctrl_partial_access.1762189935 Jun 02 01:29:15 PM PDT 24 Jun 02 01:30:27 PM PDT 24 375163100 ps
T212 /workspace/coverage/default/42.sram_ctrl_bijection.4187882348 Jun 02 01:31:57 PM PDT 24 Jun 02 01:33:17 PM PDT 24 5121596596 ps
T213 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1868153480 Jun 02 01:29:47 PM PDT 24 Jun 02 01:36:29 PM PDT 24 15914938966 ps
T99 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3310005600 Jun 02 01:31:42 PM PDT 24 Jun 02 01:31:48 PM PDT 24 179176441 ps
T214 /workspace/coverage/default/48.sram_ctrl_bijection.2279250932 Jun 02 01:32:36 PM PDT 24 Jun 02 01:33:23 PM PDT 24 2989278171 ps
T215 /workspace/coverage/default/1.sram_ctrl_mem_walk.1632871145 Jun 02 01:27:53 PM PDT 24 Jun 02 01:28:05 PM PDT 24 576611718 ps
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T216 /workspace/coverage/default/37.sram_ctrl_lc_escalation.6665341 Jun 02 01:31:15 PM PDT 24 Jun 02 01:31:22 PM PDT 24 523687302 ps
T217 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2282465038 Jun 02 01:28:26 PM PDT 24 Jun 02 01:29:02 PM PDT 24 372972287 ps
T218 /workspace/coverage/default/44.sram_ctrl_partial_access.834075585 Jun 02 01:32:10 PM PDT 24 Jun 02 01:33:08 PM PDT 24 299968429 ps
T219 /workspace/coverage/default/5.sram_ctrl_regwen.667782374 Jun 02 01:28:05 PM PDT 24 Jun 02 01:39:49 PM PDT 24 18253180667 ps
T220 /workspace/coverage/default/15.sram_ctrl_alert_test.2927032016 Jun 02 01:28:41 PM PDT 24 Jun 02 01:28:43 PM PDT 24 46996045 ps
T100 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2624888024 Jun 02 01:29:18 PM PDT 24 Jun 02 01:29:23 PM PDT 24 113036357 ps
T221 /workspace/coverage/default/47.sram_ctrl_alert_test.2476575777 Jun 02 01:32:36 PM PDT 24 Jun 02 01:32:37 PM PDT 24 60128187 ps
T222 /workspace/coverage/default/21.sram_ctrl_executable.1441542035 Jun 02 01:29:21 PM PDT 24 Jun 02 01:32:07 PM PDT 24 3146926750 ps
T223 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.86661662 Jun 02 01:31:37 PM PDT 24 Jun 02 01:35:16 PM PDT 24 4450494952 ps
T224 /workspace/coverage/default/37.sram_ctrl_executable.2260751256 Jun 02 01:31:20 PM PDT 24 Jun 02 01:33:35 PM PDT 24 1282253828 ps
T225 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.722601911 Jun 02 01:28:41 PM PDT 24 Jun 02 01:32:55 PM PDT 24 16491939104 ps
T78 /workspace/coverage/default/23.sram_ctrl_multiple_keys.2182237903 Jun 02 01:29:26 PM PDT 24 Jun 02 01:48:01 PM PDT 24 73161284579 ps
T226 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2266267839 Jun 02 01:27:44 PM PDT 24 Jun 02 01:36:55 PM PDT 24 41995511203 ps
T227 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2239661393 Jun 02 01:28:12 PM PDT 24 Jun 02 01:28:47 PM PDT 24 227098563 ps
T228 /workspace/coverage/default/31.sram_ctrl_smoke.2172903127 Jun 02 01:30:27 PM PDT 24 Jun 02 01:30:45 PM PDT 24 749030108 ps
T229 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2622590317 Jun 02 01:30:56 PM PDT 24 Jun 02 01:30:57 PM PDT 24 35580312 ps
T230 /workspace/coverage/default/37.sram_ctrl_mem_walk.1722847318 Jun 02 01:31:24 PM PDT 24 Jun 02 01:31:30 PM PDT 24 889797443 ps
T231 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3935695486 Jun 02 01:30:40 PM PDT 24 Jun 02 01:30:46 PM PDT 24 158536473 ps
T232 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3745164665 Jun 02 01:28:02 PM PDT 24 Jun 02 01:32:32 PM PDT 24 5318358247 ps
T233 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3992924917 Jun 02 01:29:20 PM PDT 24 Jun 02 01:58:02 PM PDT 24 10603738415 ps
T234 /workspace/coverage/default/21.sram_ctrl_max_throughput.3880265659 Jun 02 01:29:20 PM PDT 24 Jun 02 01:31:00 PM PDT 24 124351773 ps
T235 /workspace/coverage/default/18.sram_ctrl_smoke.4001253994 Jun 02 01:28:55 PM PDT 24 Jun 02 01:31:36 PM PDT 24 5733524146 ps
T236 /workspace/coverage/default/43.sram_ctrl_bijection.3125046680 Jun 02 01:31:55 PM PDT 24 Jun 02 01:32:37 PM PDT 24 5984568911 ps
T237 /workspace/coverage/default/34.sram_ctrl_executable.693011919 Jun 02 01:30:55 PM PDT 24 Jun 02 01:44:15 PM PDT 24 1697489131 ps
T238 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1186974247 Jun 02 01:31:27 PM PDT 24 Jun 02 01:35:04 PM PDT 24 8562592382 ps
T239 /workspace/coverage/default/17.sram_ctrl_alert_test.405019385 Jun 02 01:28:54 PM PDT 24 Jun 02 01:28:55 PM PDT 24 21994078 ps
T240 /workspace/coverage/default/8.sram_ctrl_partial_access.1423635206 Jun 02 01:28:11 PM PDT 24 Jun 02 01:29:35 PM PDT 24 548830261 ps
T241 /workspace/coverage/default/11.sram_ctrl_multiple_keys.4212450121 Jun 02 01:28:22 PM PDT 24 Jun 02 01:28:43 PM PDT 24 6059187790 ps
T150 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.570924051 Jun 02 01:28:04 PM PDT 24 Jun 02 01:33:45 PM PDT 24 50769591975 ps
T242 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3678680102 Jun 02 01:31:25 PM PDT 24 Jun 02 01:33:22 PM PDT 24 230766961 ps
T243 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.544609991 Jun 02 01:31:49 PM PDT 24 Jun 02 01:31:53 PM PDT 24 832671314 ps
T244 /workspace/coverage/default/37.sram_ctrl_regwen.419454988 Jun 02 01:31:27 PM PDT 24 Jun 02 01:38:44 PM PDT 24 9291323521 ps
T151 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3493901736 Jun 02 01:32:50 PM PDT 24 Jun 02 01:37:44 PM PDT 24 45828309651 ps
T245 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3503981339 Jun 02 01:30:23 PM PDT 24 Jun 02 01:30:29 PM PDT 24 172099106 ps
T246 /workspace/coverage/default/8.sram_ctrl_multiple_keys.487336198 Jun 02 01:28:16 PM PDT 24 Jun 02 01:42:16 PM PDT 24 11073739802 ps
T247 /workspace/coverage/default/28.sram_ctrl_lc_escalation.1613916488 Jun 02 01:30:13 PM PDT 24 Jun 02 01:30:14 PM PDT 24 26938510 ps
T248 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2862774336 Jun 02 01:28:12 PM PDT 24 Jun 02 01:28:15 PM PDT 24 96268080 ps
T143 /workspace/coverage/default/27.sram_ctrl_regwen.4077604072 Jun 02 01:30:01 PM PDT 24 Jun 02 01:30:43 PM PDT 24 9353965262 ps
T21 /workspace/coverage/default/0.sram_ctrl_sec_cm.665329350 Jun 02 01:27:52 PM PDT 24 Jun 02 01:27:55 PM PDT 24 910703666 ps
T36 /workspace/coverage/default/48.sram_ctrl_partial_access.3746031274 Jun 02 01:32:36 PM PDT 24 Jun 02 01:33:11 PM PDT 24 392789587 ps
T37 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2280689405 Jun 02 01:30:08 PM PDT 24 Jun 02 01:30:12 PM PDT 24 191730753 ps
T38 /workspace/coverage/default/33.sram_ctrl_partial_access.4005642860 Jun 02 01:30:38 PM PDT 24 Jun 02 01:30:45 PM PDT 24 287621990 ps
T39 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2980038283 Jun 02 01:28:27 PM PDT 24 Jun 02 01:31:06 PM PDT 24 2195281953 ps
T40 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1311971338 Jun 02 01:29:34 PM PDT 24 Jun 02 01:29:40 PM PDT 24 201869475 ps
T41 /workspace/coverage/default/6.sram_ctrl_max_throughput.2394959143 Jun 02 01:28:10 PM PDT 24 Jun 02 01:30:03 PM PDT 24 261900150 ps
T42 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1851402681 Jun 02 01:31:55 PM PDT 24 Jun 02 01:35:54 PM PDT 24 15258283460 ps
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T44 /workspace/coverage/default/42.sram_ctrl_multiple_keys.1719018427 Jun 02 01:31:53 PM PDT 24 Jun 02 01:47:10 PM PDT 24 10002196993 ps
T249 /workspace/coverage/default/27.sram_ctrl_bijection.1368215084 Jun 02 01:29:55 PM PDT 24 Jun 02 01:30:48 PM PDT 24 2583103263 ps
T250 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.95210199 Jun 02 01:28:38 PM PDT 24 Jun 02 01:30:54 PM PDT 24 591056407 ps
T251 /workspace/coverage/default/34.sram_ctrl_lc_escalation.2614734727 Jun 02 01:30:59 PM PDT 24 Jun 02 01:31:07 PM PDT 24 1459562073 ps
T252 /workspace/coverage/default/5.sram_ctrl_partial_access.3205766285 Jun 02 01:28:05 PM PDT 24 Jun 02 01:28:12 PM PDT 24 366588636 ps
T253 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2771655574 Jun 02 01:28:05 PM PDT 24 Jun 02 01:29:54 PM PDT 24 574185411 ps
T254 /workspace/coverage/default/19.sram_ctrl_multiple_keys.1648613879 Jun 02 01:29:02 PM PDT 24 Jun 02 01:42:16 PM PDT 24 11820389664 ps
T79 /workspace/coverage/default/43.sram_ctrl_multiple_keys.721799805 Jun 02 01:31:55 PM PDT 24 Jun 02 01:42:45 PM PDT 24 2331611539 ps
T255 /workspace/coverage/default/2.sram_ctrl_ram_cfg.600961114 Jun 02 01:27:50 PM PDT 24 Jun 02 01:27:51 PM PDT 24 28377820 ps
T256 /workspace/coverage/default/29.sram_ctrl_executable.2984207140 Jun 02 01:30:16 PM PDT 24 Jun 02 01:39:50 PM PDT 24 3123083368 ps
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T258 /workspace/coverage/default/36.sram_ctrl_partial_access.1963050870 Jun 02 01:31:08 PM PDT 24 Jun 02 01:31:31 PM PDT 24 358114132 ps
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T261 /workspace/coverage/default/28.sram_ctrl_mem_walk.2206970059 Jun 02 01:30:10 PM PDT 24 Jun 02 01:30:17 PM PDT 24 1295955841 ps
T262 /workspace/coverage/default/24.sram_ctrl_max_throughput.1803349904 Jun 02 01:29:33 PM PDT 24 Jun 02 01:29:36 PM PDT 24 89644613 ps
T263 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.593262690 Jun 02 01:32:03 PM PDT 24 Jun 02 01:34:15 PM PDT 24 11806498420 ps
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T265 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3587416227 Jun 02 01:27:51 PM PDT 24 Jun 02 01:27:57 PM PDT 24 613401723 ps
T266 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.209959015 Jun 02 01:32:22 PM PDT 24 Jun 02 01:32:25 PM PDT 24 50612691 ps
T267 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2589620876 Jun 02 01:32:43 PM PDT 24 Jun 02 01:32:47 PM PDT 24 53925524 ps
T268 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1042556543 Jun 02 01:27:52 PM PDT 24 Jun 02 01:28:12 PM PDT 24 335046445 ps
T269 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2521175783 Jun 02 01:32:16 PM PDT 24 Jun 02 01:32:17 PM PDT 24 132771216 ps
T270 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3857877826 Jun 02 01:32:52 PM PDT 24 Jun 02 01:36:23 PM PDT 24 16418631875 ps
T271 /workspace/coverage/default/36.sram_ctrl_mem_walk.2722692428 Jun 02 01:31:08 PM PDT 24 Jun 02 01:31:19 PM PDT 24 460212949 ps
T272 /workspace/coverage/default/41.sram_ctrl_mem_walk.586404936 Jun 02 01:31:47 PM PDT 24 Jun 02 01:31:53 PM PDT 24 628530764 ps
T273 /workspace/coverage/default/28.sram_ctrl_max_throughput.3798846251 Jun 02 01:30:09 PM PDT 24 Jun 02 01:30:12 PM PDT 24 155156719 ps
T274 /workspace/coverage/default/27.sram_ctrl_max_throughput.3019562750 Jun 02 01:29:56 PM PDT 24 Jun 02 01:29:58 PM PDT 24 158579811 ps
T275 /workspace/coverage/default/25.sram_ctrl_executable.1555047164 Jun 02 01:29:53 PM PDT 24 Jun 02 01:29:56 PM PDT 24 898766999 ps
T276 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2161818856 Jun 02 01:28:18 PM PDT 24 Jun 02 01:34:54 PM PDT 24 75419622885 ps
T277 /workspace/coverage/default/8.sram_ctrl_smoke.2365579741 Jun 02 01:28:11 PM PDT 24 Jun 02 01:28:27 PM PDT 24 1025576240 ps
T278 /workspace/coverage/default/32.sram_ctrl_regwen.2457717150 Jun 02 01:30:40 PM PDT 24 Jun 02 01:37:21 PM PDT 24 5026064773 ps
T279 /workspace/coverage/default/1.sram_ctrl_alert_test.3863673198 Jun 02 01:27:50 PM PDT 24 Jun 02 01:27:51 PM PDT 24 89854546 ps
T280 /workspace/coverage/default/44.sram_ctrl_lc_escalation.4257440559 Jun 02 01:32:12 PM PDT 24 Jun 02 01:32:18 PM PDT 24 948679741 ps
T281 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1430770665 Jun 02 01:32:28 PM PDT 24 Jun 02 01:32:32 PM PDT 24 104687955 ps
T282 /workspace/coverage/default/10.sram_ctrl_mem_walk.3572180786 Jun 02 01:28:18 PM PDT 24 Jun 02 01:28:27 PM PDT 24 135273041 ps
T283 /workspace/coverage/default/9.sram_ctrl_bijection.723869013 Jun 02 01:28:17 PM PDT 24 Jun 02 01:29:22 PM PDT 24 4374840914 ps
T284 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3779211621 Jun 02 01:28:35 PM PDT 24 Jun 02 01:28:36 PM PDT 24 25921124 ps
T285 /workspace/coverage/default/40.sram_ctrl_regwen.335391970 Jun 02 01:31:41 PM PDT 24 Jun 02 01:51:47 PM PDT 24 131104256613 ps
T22 /workspace/coverage/default/2.sram_ctrl_sec_cm.1421871106 Jun 02 01:27:56 PM PDT 24 Jun 02 01:27:58 PM PDT 24 931120410 ps
T286 /workspace/coverage/default/6.sram_ctrl_lc_escalation.2349763369 Jun 02 01:28:03 PM PDT 24 Jun 02 01:28:08 PM PDT 24 1050964889 ps
T287 /workspace/coverage/default/25.sram_ctrl_ram_cfg.988868094 Jun 02 01:29:49 PM PDT 24 Jun 02 01:29:50 PM PDT 24 49401830 ps
T288 /workspace/coverage/default/32.sram_ctrl_mem_walk.4012194923 Jun 02 01:30:38 PM PDT 24 Jun 02 01:30:50 PM PDT 24 1343648213 ps
T289 /workspace/coverage/default/7.sram_ctrl_max_throughput.3555816436 Jun 02 01:28:04 PM PDT 24 Jun 02 01:28:45 PM PDT 24 293704767 ps
T290 /workspace/coverage/default/6.sram_ctrl_bijection.2162915976 Jun 02 01:28:04 PM PDT 24 Jun 02 01:28:39 PM PDT 24 5264342137 ps
T291 /workspace/coverage/default/11.sram_ctrl_bijection.3451199114 Jun 02 01:28:17 PM PDT 24 Jun 02 01:29:04 PM PDT 24 10437484433 ps
T292 /workspace/coverage/default/0.sram_ctrl_max_throughput.1135309463 Jun 02 01:27:45 PM PDT 24 Jun 02 01:27:59 PM PDT 24 124401019 ps
T293 /workspace/coverage/default/25.sram_ctrl_multiple_keys.3069963715 Jun 02 01:29:45 PM PDT 24 Jun 02 01:34:54 PM PDT 24 1365351331 ps
T294 /workspace/coverage/default/35.sram_ctrl_regwen.1648015388 Jun 02 01:31:00 PM PDT 24 Jun 02 01:39:46 PM PDT 24 7875454401 ps
T295 /workspace/coverage/default/41.sram_ctrl_max_throughput.510204787 Jun 02 01:31:48 PM PDT 24 Jun 02 01:33:29 PM PDT 24 125723757 ps
T296 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2308854348 Jun 02 01:32:10 PM PDT 24 Jun 02 01:38:14 PM PDT 24 5363029177 ps
T297 /workspace/coverage/default/23.sram_ctrl_partial_access.2200549780 Jun 02 01:29:29 PM PDT 24 Jun 02 01:29:33 PM PDT 24 250449122 ps
T298 /workspace/coverage/default/10.sram_ctrl_max_throughput.1291781055 Jun 02 01:28:22 PM PDT 24 Jun 02 01:30:35 PM PDT 24 511540961 ps
T299 /workspace/coverage/default/4.sram_ctrl_partial_access.736965065 Jun 02 01:28:00 PM PDT 24 Jun 02 01:29:40 PM PDT 24 190229088 ps
T300 /workspace/coverage/default/11.sram_ctrl_executable.1426868123 Jun 02 01:28:32 PM PDT 24 Jun 02 01:47:54 PM PDT 24 28412485760 ps
T301 /workspace/coverage/default/23.sram_ctrl_bijection.907353757 Jun 02 01:29:27 PM PDT 24 Jun 02 01:30:45 PM PDT 24 82560469756 ps
T302 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1005890472 Jun 02 01:28:02 PM PDT 24 Jun 02 01:28:03 PM PDT 24 57270444 ps
T303 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2762963454 Jun 02 01:29:09 PM PDT 24 Jun 02 01:29:13 PM PDT 24 132787167 ps
T304 /workspace/coverage/default/9.sram_ctrl_mem_walk.3513248519 Jun 02 01:28:19 PM PDT 24 Jun 02 01:28:29 PM PDT 24 137055547 ps
T305 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3285948099 Jun 02 01:32:13 PM PDT 24 Jun 02 01:38:40 PM PDT 24 6367673742 ps
T306 /workspace/coverage/default/34.sram_ctrl_mem_walk.3416517783 Jun 02 01:31:00 PM PDT 24 Jun 02 01:31:09 PM PDT 24 1741932996 ps
T307 /workspace/coverage/default/48.sram_ctrl_regwen.1350974360 Jun 02 01:32:43 PM PDT 24 Jun 02 01:34:45 PM PDT 24 1229506525 ps
T308 /workspace/coverage/default/37.sram_ctrl_alert_test.728502342 Jun 02 01:31:26 PM PDT 24 Jun 02 01:31:27 PM PDT 24 17725165 ps
T309 /workspace/coverage/default/21.sram_ctrl_mem_walk.3695044520 Jun 02 01:29:20 PM PDT 24 Jun 02 01:29:25 PM PDT 24 182767244 ps
T310 /workspace/coverage/default/45.sram_ctrl_executable.1252703200 Jun 02 01:32:23 PM PDT 24 Jun 02 01:57:11 PM PDT 24 6112955817 ps
T311 /workspace/coverage/default/48.sram_ctrl_max_throughput.2545835718 Jun 02 01:32:43 PM PDT 24 Jun 02 01:34:26 PM PDT 24 1912990057 ps
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