Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	24600210	1			T1	4902		T2	8650		T3	51200
triple_byte_access	2142644	1			T4	355		T5	239		T9	117
halfword_access	3218132	1			T4	514		T5	433		T9	151
byte_access	4300300	1			T4	699		T5	818		T9	234
zero_access	1082040	1			T4	177		T5	416		T9	52

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17622699

1

T1

2469

T2

4322

T3

25600

auto[1]

17720627

1

T1

2433

T2

4328

T3

25600

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	12256440	1			T1	2469		T2	4322		T3	25600
auto[0]	triple_byte_access	1067665	1			T4	166		T5	46		T9	58
auto[0]	halfword_access	1605726	1			T4	252		T5	131		T9	83
auto[0]	byte_access	2148285	1			T4	357		T5	388		T9	114
auto[0]	zero_access	544583	1			T4	90		T5	304		T9	29
auto[1]	word_access	12343770	1			T1	2433		T2	4328		T3	25600
auto[1]	triple_byte_access	1074979	1			T4	189		T5	193		T9	59
auto[1]	halfword_access	1612406	1			T4	262		T5	302		T9	68
auto[1]	byte_access	2152015	1			T4	342		T5	430		T9	120
auto[1]	zero_access	537457	1			T4	87		T5	112		T9	23