Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	87977654	1			T1	208724		T3	45056		T4	513130
instr_valid_dis	71871305	1			T1	208724		T3	45056		T4	140690
instr_en	11097117	1			T4	339112		T5	276358		T29	30698

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5290884	1			T4	130020		T5	57788		T29	6848
sram_ifetch_valid_disable	72121560	1			T1	208724		T3	45056		T4	265976
sram_ifetch_enable	10565210	1			T4	117134		T5	124424		T29	177440

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	87977654	1			T1	208724		T3	45056		T4	513130
hw_debug_en_valid_off	71488734	1			T1	208724		T3	45056		T4	133384
hw_debug_en_on	10670968	1			T4	373794		T5	112762		T29	93166

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	72121560	1			T1	208724		T3	45056		T4	265976
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	65864131	1			T1	208724		T3	45056		T4	82654
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4209251	1			T4	163546		T5	94234		T22	104792
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	1708076	1			T4	13552		T5	57788		T29	6848
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	700814	1			T29	6848		T23	25980		T48	1052
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	629894	1			T5	57788		T153	16944		T161	61474
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2420930	1			T4	110646		T22	55692		T23	238
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	946312	1			T23	238		T85	2906		T133	41698
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1111930	1			T4	110646		T22	55692		T49	6378
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4404756	1			T4	185492		T5	72034		T29	50694
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1628912	1			T4	34318		T29	50694		T23	105874
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1931950	1			T4	137456		T5	72034		T72	9474

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4569358	1			T4	59098		T5	124336		T29	30698
lc_exec_en	3845282	1			T4	77656		T5	40728		T29	42472
valid_exec_dis	69131550	1			T1	208724		T3	45056		T4	138390
invalid_exec_dis	15856094	1			T4	247154		T5	182212		T29	184288