Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.27 99.18 95.41 100.00 100.00 96.12 99.56 97.62


Total tests in report: 884
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.37 82.37 96.95 96.95 81.77 81.77 64.43 64.43 90.48 90.48 91.20 91.20 94.53 94.53 57.22 57.22 /workspace/coverage/default/34.sram_ctrl_regwen.2261254033
87.94 5.57 98.10 1.16 84.65 2.88 84.25 19.82 100.00 9.52 93.75 2.55 94.68 0.15 60.15 2.93 /workspace/coverage/default/39.sram_ctrl_lc_escalation.1473267800
92.51 4.56 98.60 0.50 88.25 3.60 86.68 2.43 100.00 0.00 94.44 0.69 96.75 2.07 82.82 22.67 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.814052504
94.48 1.98 98.76 0.17 88.37 0.12 97.93 11.25 100.00 0.00 94.91 0.46 96.75 0.00 84.64 1.83 /workspace/coverage/default/47.sram_ctrl_executable.3845821742
95.45 0.97 98.93 0.17 89.33 0.96 98.14 0.21 100.00 0.00 95.60 0.69 96.75 0.00 89.40 4.75 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3171085571
96.03 0.58 99.09 0.17 91.13 1.80 98.57 0.43 100.00 0.00 96.30 0.69 97.34 0.59 89.76 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.1593391324
96.36 0.33 99.09 0.00 91.13 0.00 98.57 0.00 100.00 0.00 96.30 0.00 97.49 0.15 91.96 2.19 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2853130882
96.57 0.21 99.09 0.00 91.13 0.00 98.57 0.00 100.00 0.00 96.30 0.00 97.49 0.00 93.42 1.46 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3570713620
96.76 0.19 99.09 0.00 91.49 0.36 99.00 0.43 100.00 0.00 96.30 0.00 97.49 0.00 93.97 0.55 /workspace/coverage/default/18.sram_ctrl_alert_test.3731838956
96.92 0.16 99.09 0.00 91.49 0.00 99.07 0.07 100.00 0.00 96.30 0.00 98.38 0.89 94.15 0.18 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3554192756
97.07 0.15 99.09 0.00 91.61 0.12 99.07 0.00 100.00 0.00 96.30 0.00 98.38 0.00 95.06 0.91 /workspace/coverage/default/30.sram_ctrl_regwen.2706234890
97.20 0.13 99.09 0.00 91.61 0.00 99.07 0.00 100.00 0.00 96.30 0.00 98.38 0.00 95.98 0.91 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2456348789
97.33 0.13 99.09 0.00 91.61 0.00 99.07 0.00 100.00 0.00 96.30 0.00 99.26 0.89 95.98 0.00 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1619615147
97.45 0.12 99.17 0.08 91.61 0.00 99.86 0.79 100.00 0.00 96.30 0.00 99.26 0.00 95.98 0.00 /workspace/coverage/default/42.sram_ctrl_ram_cfg.477981744
97.53 0.08 99.17 0.00 91.61 0.00 99.86 0.00 100.00 0.00 96.30 0.00 99.26 0.00 96.53 0.55 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2319526964
97.61 0.08 99.17 0.00 91.97 0.36 99.86 0.00 100.00 0.00 96.30 0.00 99.26 0.00 96.71 0.18 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2014422291
97.67 0.06 99.17 0.00 91.97 0.00 99.93 0.07 100.00 0.00 96.30 0.00 99.26 0.00 97.07 0.37 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1249736762
97.72 0.05 99.17 0.00 91.97 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.26 0.00 97.44 0.37 /workspace/coverage/default/40.sram_ctrl_executable.4277553625
97.75 0.03 99.17 0.00 91.97 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.26 0.00 97.62 0.18 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1455757386
97.77 0.02 99.17 0.00 91.97 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.41 0.15 97.62 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1544716060
97.79 0.02 99.17 0.00 91.97 0.00 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.15 97.62 0.00 /workspace/coverage/default/12.sram_ctrl_regwen.4072032990
97.81 0.02 99.17 0.00 92.09 0.12 99.93 0.00 100.00 0.00 96.30 0.00 99.56 0.00 97.62 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1644287335
97.82 0.01 99.17 0.00 92.09 0.00 100.00 0.07 100.00 0.00 96.30 0.00 99.56 0.00 97.62 0.00 /workspace/coverage/default/14.sram_ctrl_partial_access.1965044008

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3781196873
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3852594098
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3160668575
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3501904105
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3936474855
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2021458275
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2758374859
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3744091199
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2886868701
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2926825092
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2406643145
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2737644831
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3246543720
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1395291323
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2612742529
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3920691699
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1617348810
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3258004042
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4241957699
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.64984464
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1885826250
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2848993678
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3262715493
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2405150162
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2449617154
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3085958647
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2704550611
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1683608826
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2568533550
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1733934199
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.791900848
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3737991090
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1252510888
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.813474579
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3767413866
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2322555983
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4136511264
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.614213744
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.571041753
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2856724557
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4185739444
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1002242724
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3290830241
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2669645694
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1996266310
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1509312283
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3248081195
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.345066061
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2302551054
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2225971332
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.769611940
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1027886924
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1389487154
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2529799182
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3374728923
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2776186649
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3274322537
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3352898938
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2200167781
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.28656658
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3934162204
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2746237355
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4164588099
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3998548984
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3626620480
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3805685029
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3768341782
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1899481877
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2378847742
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.806274505
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3456838689
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.300855909
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3109448920
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1394861997
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3859562080
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1815585224
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.933145863
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4244889986
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3175170508
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2078043244
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3340528922
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3297048301
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3013041354
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3793024621
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3312590767
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2317155480
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4153939048
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.794003679
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3442199985
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3021911619
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.677807684
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4290295072
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1000085033
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3436962693
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1701944097
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4274253718
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1559842161
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1529524130
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2198728087
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3001552164
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3405537250
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3442530870
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4212914991
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1860889694
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.679732022
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2379188376
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3623644295
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.494184741
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.884850449
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3933305216
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2324469032
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.461396646
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2814964039
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.526241214
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2720610820
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1853404583
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3258736901
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.852371155
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2633711799
/workspace/coverage/default/0.sram_ctrl_alert_test.2313345192
/workspace/coverage/default/0.sram_ctrl_bijection.1653524893
/workspace/coverage/default/0.sram_ctrl_executable.395792952
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3089467532
/workspace/coverage/default/0.sram_ctrl_max_throughput.3546096655
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1862472891
/workspace/coverage/default/0.sram_ctrl_mem_walk.3648957783
/workspace/coverage/default/0.sram_ctrl_multiple_keys.835836299
/workspace/coverage/default/0.sram_ctrl_partial_access.3579270352
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2572304516
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3534408347
/workspace/coverage/default/0.sram_ctrl_regwen.589527364
/workspace/coverage/default/0.sram_ctrl_smoke.3030745919
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2840403965
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1032260460
/workspace/coverage/default/1.sram_ctrl_alert_test.1401244375
/workspace/coverage/default/1.sram_ctrl_bijection.1518932647
/workspace/coverage/default/1.sram_ctrl_executable.2097002596
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3231284676
/workspace/coverage/default/1.sram_ctrl_max_throughput.2864074443
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3396041616
/workspace/coverage/default/1.sram_ctrl_mem_walk.2654029718
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3646108639
/workspace/coverage/default/1.sram_ctrl_partial_access.3338815518
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4274030240
/workspace/coverage/default/1.sram_ctrl_ram_cfg.648757743
/workspace/coverage/default/1.sram_ctrl_regwen.3460447627
/workspace/coverage/default/1.sram_ctrl_sec_cm.3383753361
/workspace/coverage/default/1.sram_ctrl_smoke.3132080870
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1050444766
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3591853976
/workspace/coverage/default/10.sram_ctrl_alert_test.2984029523
/workspace/coverage/default/10.sram_ctrl_bijection.1573307965
/workspace/coverage/default/10.sram_ctrl_executable.1368703049
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2708044099
/workspace/coverage/default/10.sram_ctrl_max_throughput.764938588
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4109117601
/workspace/coverage/default/10.sram_ctrl_mem_walk.1249787426
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2204179655
/workspace/coverage/default/10.sram_ctrl_partial_access.3579687191
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2744404341
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1794728249
/workspace/coverage/default/10.sram_ctrl_regwen.3218255682
/workspace/coverage/default/10.sram_ctrl_smoke.1477645401
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1671719462
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4203868828
/workspace/coverage/default/11.sram_ctrl_alert_test.1589119758
/workspace/coverage/default/11.sram_ctrl_bijection.1176641301
/workspace/coverage/default/11.sram_ctrl_executable.1772321953
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1749952984
/workspace/coverage/default/11.sram_ctrl_max_throughput.1736719284
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2392414389
/workspace/coverage/default/11.sram_ctrl_mem_walk.1486954880
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3122785367
/workspace/coverage/default/11.sram_ctrl_partial_access.915263349
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3433250218
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3819379938
/workspace/coverage/default/11.sram_ctrl_regwen.47340508
/workspace/coverage/default/11.sram_ctrl_smoke.889818234
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1406083228
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2613958706
/workspace/coverage/default/12.sram_ctrl_alert_test.255853483
/workspace/coverage/default/12.sram_ctrl_bijection.2245860502
/workspace/coverage/default/12.sram_ctrl_executable.3715365461
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3529053593
/workspace/coverage/default/12.sram_ctrl_max_throughput.118529240
/workspace/coverage/default/12.sram_ctrl_mem_walk.3703298684
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2553494032
/workspace/coverage/default/12.sram_ctrl_partial_access.2499154454
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.118283431
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3410070037
/workspace/coverage/default/12.sram_ctrl_smoke.3436169083
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3459467336
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2279170538
/workspace/coverage/default/13.sram_ctrl_alert_test.880145831
/workspace/coverage/default/13.sram_ctrl_bijection.3003515495
/workspace/coverage/default/13.sram_ctrl_executable.1795063080
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2376873482
/workspace/coverage/default/13.sram_ctrl_max_throughput.753766479
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2626614848
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/workspace/coverage/default/6.sram_ctrl_lc_escalation.993896428
/workspace/coverage/default/6.sram_ctrl_max_throughput.3364453757
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2359976312
/workspace/coverage/default/6.sram_ctrl_mem_walk.1409898909
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2121809011
/workspace/coverage/default/6.sram_ctrl_partial_access.1597368543
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1394698988
/workspace/coverage/default/6.sram_ctrl_regwen.2651200315
/workspace/coverage/default/6.sram_ctrl_smoke.1457538161
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2280772763
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.552031433
/workspace/coverage/default/7.sram_ctrl_alert_test.348455058
/workspace/coverage/default/7.sram_ctrl_bijection.3770399341
/workspace/coverage/default/7.sram_ctrl_executable.102342583
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2074065328
/workspace/coverage/default/7.sram_ctrl_max_throughput.2513061456
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1856912289
/workspace/coverage/default/7.sram_ctrl_mem_walk.1249801756
/workspace/coverage/default/7.sram_ctrl_multiple_keys.340311080
/workspace/coverage/default/7.sram_ctrl_partial_access.1862198148
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2078242107
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2646759549
/workspace/coverage/default/7.sram_ctrl_regwen.745103148
/workspace/coverage/default/7.sram_ctrl_smoke.2814517981
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3473746968
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2726371961
/workspace/coverage/default/8.sram_ctrl_alert_test.1343240112
/workspace/coverage/default/8.sram_ctrl_bijection.3644098117
/workspace/coverage/default/8.sram_ctrl_executable.862864248
/workspace/coverage/default/8.sram_ctrl_lc_escalation.969816100
/workspace/coverage/default/8.sram_ctrl_max_throughput.76149454
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4043799350
/workspace/coverage/default/8.sram_ctrl_mem_walk.1512705009
/workspace/coverage/default/8.sram_ctrl_multiple_keys.4062948695
/workspace/coverage/default/8.sram_ctrl_partial_access.3151501822
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1698339345
/workspace/coverage/default/8.sram_ctrl_ram_cfg.116118847
/workspace/coverage/default/8.sram_ctrl_regwen.3566744724
/workspace/coverage/default/8.sram_ctrl_smoke.2604298212
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.933555631
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4120695850
/workspace/coverage/default/9.sram_ctrl_alert_test.188799048
/workspace/coverage/default/9.sram_ctrl_bijection.2954431144
/workspace/coverage/default/9.sram_ctrl_executable.3678416697
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2013143921
/workspace/coverage/default/9.sram_ctrl_max_throughput.955005758
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.422259494
/workspace/coverage/default/9.sram_ctrl_mem_walk.2720800897
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2459664916
/workspace/coverage/default/9.sram_ctrl_partial_access.3034170004
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3928224511
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2696069782
/workspace/coverage/default/9.sram_ctrl_regwen.2643698964
/workspace/coverage/default/9.sram_ctrl_smoke.2870418321
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.338382091
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3246313138



Total test records in report: 884
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.745953137 Jun 04 01:27:21 PM PDT 24 Jun 04 01:30:33 PM PDT 24 31058793427 ps
T2 /workspace/coverage/default/43.sram_ctrl_alert_test.244586584 Jun 04 01:26:58 PM PDT 24 Jun 04 01:27:00 PM PDT 24 15698312 ps
T3 /workspace/coverage/default/15.sram_ctrl_bijection.3464801400 Jun 04 01:21:52 PM PDT 24 Jun 04 01:22:35 PM PDT 24 9251352758 ps
T4 /workspace/coverage/default/47.sram_ctrl_executable.3845821742 Jun 04 01:27:37 PM PDT 24 Jun 04 01:51:47 PM PDT 24 9765415145 ps
T10 /workspace/coverage/default/20.sram_ctrl_bijection.1032253495 Jun 04 01:22:35 PM PDT 24 Jun 04 01:23:40 PM PDT 24 6824002598 ps
T6 /workspace/coverage/default/47.sram_ctrl_max_throughput.3915700226 Jun 04 01:27:37 PM PDT 24 Jun 04 01:28:16 PM PDT 24 180941498 ps
T5 /workspace/coverage/default/34.sram_ctrl_regwen.2261254033 Jun 04 01:25:17 PM PDT 24 Jun 04 01:39:45 PM PDT 24 81376259202 ps
T11 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1748118186 Jun 04 01:25:40 PM PDT 24 Jun 04 01:25:44 PM PDT 24 340778087 ps
T12 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3763977214 Jun 04 01:24:57 PM PDT 24 Jun 04 01:29:28 PM PDT 24 48265261083 ps
T13 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.358504636 Jun 04 01:25:32 PM PDT 24 Jun 04 01:30:31 PM PDT 24 5448908744 ps
T14 /workspace/coverage/default/10.sram_ctrl_smoke.1477645401 Jun 04 01:21:16 PM PDT 24 Jun 04 01:21:39 PM PDT 24 307427578 ps
T16 /workspace/coverage/default/36.sram_ctrl_bijection.2597871604 Jun 04 01:25:33 PM PDT 24 Jun 04 01:26:08 PM PDT 24 2212817702 ps
T51 /workspace/coverage/default/14.sram_ctrl_partial_access.1965044008 Jun 04 01:21:44 PM PDT 24 Jun 04 01:22:04 PM PDT 24 371264934 ps
T46 /workspace/coverage/default/31.sram_ctrl_partial_access.255853276 Jun 04 01:24:27 PM PDT 24 Jun 04 01:24:55 PM PDT 24 393174712 ps
T15 /workspace/coverage/default/6.sram_ctrl_multiple_keys.2121809011 Jun 04 01:21:06 PM PDT 24 Jun 04 01:44:21 PM PDT 24 19871122814 ps
T60 /workspace/coverage/default/29.sram_ctrl_bijection.4050000368 Jun 04 01:24:07 PM PDT 24 Jun 04 01:24:31 PM PDT 24 11979643834 ps
T29 /workspace/coverage/default/36.sram_ctrl_regwen.4098582070 Jun 04 01:25:32 PM PDT 24 Jun 04 01:44:25 PM PDT 24 99952808007 ps
T52 /workspace/coverage/default/7.sram_ctrl_partial_access.1862198148 Jun 04 01:21:04 PM PDT 24 Jun 04 01:21:28 PM PDT 24 4800476360 ps
T83 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2853130882 Jun 04 01:21:01 PM PDT 24 Jun 04 01:30:27 PM PDT 24 21568964444 ps
T47 /workspace/coverage/default/5.sram_ctrl_mem_walk.4244365294 Jun 04 01:20:58 PM PDT 24 Jun 04 01:21:10 PM PDT 24 466037428 ps
T7 /workspace/coverage/default/39.sram_ctrl_lc_escalation.1473267800 Jun 04 01:26:06 PM PDT 24 Jun 04 01:26:13 PM PDT 24 1332410624 ps
T165 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.710965932 Jun 04 01:23:25 PM PDT 24 Jun 04 01:25:59 PM PDT 24 172343081 ps
T163 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2419934734 Jun 04 01:26:44 PM PDT 24 Jun 04 01:45:01 PM PDT 24 44284000003 ps
T84 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3442289378 Jun 04 01:25:04 PM PDT 24 Jun 04 01:40:17 PM PDT 24 49105105875 ps
T32 /workspace/coverage/default/48.sram_ctrl_ram_cfg.1503160665 Jun 04 01:27:52 PM PDT 24 Jun 04 01:27:53 PM PDT 24 86827102 ps
T28 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.814052504 Jun 04 01:27:58 PM PDT 24 Jun 04 01:28:04 PM PDT 24 326933732 ps
T66 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3658392542 Jun 04 01:23:47 PM PDT 24 Jun 04 01:25:49 PM PDT 24 1629190443 ps
T67 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2918994818 Jun 04 01:22:02 PM PDT 24 Jun 04 01:22:05 PM PDT 24 95262518 ps
T68 /workspace/coverage/default/7.sram_ctrl_mem_walk.1249801756 Jun 04 01:21:00 PM PDT 24 Jun 04 01:21:06 PM PDT 24 558247497 ps
T8 /workspace/coverage/default/16.sram_ctrl_lc_escalation.4193430565 Jun 04 01:22:04 PM PDT 24 Jun 04 01:22:10 PM PDT 24 565369885 ps
T69 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3149320007 Jun 04 01:23:19 PM PDT 24 Jun 04 01:25:44 PM PDT 24 579811917 ps
T17 /workspace/coverage/default/18.sram_ctrl_alert_test.3731838956 Jun 04 01:22:27 PM PDT 24 Jun 04 01:22:29 PM PDT 24 92973880 ps
T70 /workspace/coverage/default/42.sram_ctrl_max_throughput.1480196295 Jun 04 01:26:42 PM PDT 24 Jun 04 01:27:01 PM PDT 24 346622586 ps
T22 /workspace/coverage/default/49.sram_ctrl_regwen.2697738887 Jun 04 01:27:59 PM PDT 24 Jun 04 01:40:22 PM PDT 24 10810324634 ps
T71 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.166973981 Jun 04 01:26:59 PM PDT 24 Jun 04 01:28:44 PM PDT 24 151444883 ps
T118 /workspace/coverage/default/37.sram_ctrl_max_throughput.3937396411 Jun 04 01:25:48 PM PDT 24 Jun 04 01:27:06 PM PDT 24 123517015 ps
T119 /workspace/coverage/default/9.sram_ctrl_max_throughput.955005758 Jun 04 01:21:19 PM PDT 24 Jun 04 01:22:10 PM PDT 24 191891850 ps
T23 /workspace/coverage/default/30.sram_ctrl_regwen.2706234890 Jun 04 01:24:31 PM PDT 24 Jun 04 01:46:38 PM PDT 24 26330118015 ps
T33 /workspace/coverage/default/42.sram_ctrl_ram_cfg.477981744 Jun 04 01:26:52 PM PDT 24 Jun 04 01:26:55 PM PDT 24 215242631 ps
T18 /workspace/coverage/default/30.sram_ctrl_alert_test.3594089837 Jun 04 01:24:35 PM PDT 24 Jun 04 01:24:37 PM PDT 24 22538740 ps
T24 /workspace/coverage/default/19.sram_ctrl_regwen.150136300 Jun 04 01:22:25 PM PDT 24 Jun 04 01:31:56 PM PDT 24 2607022772 ps
T166 /workspace/coverage/default/34.sram_ctrl_bijection.3745231253 Jun 04 01:25:10 PM PDT 24 Jun 04 01:25:48 PM PDT 24 636345272 ps
T167 /workspace/coverage/default/33.sram_ctrl_mem_walk.2717436557 Jun 04 01:25:05 PM PDT 24 Jun 04 01:25:11 PM PDT 24 903402306 ps
T168 /workspace/coverage/default/32.sram_ctrl_bijection.3578541355 Jun 04 01:24:41 PM PDT 24 Jun 04 01:25:38 PM PDT 24 877076580 ps
T169 /workspace/coverage/default/23.sram_ctrl_mem_walk.415476779 Jun 04 01:23:09 PM PDT 24 Jun 04 01:23:15 PM PDT 24 233611415 ps
T131 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2390578901 Jun 04 01:24:07 PM PDT 24 Jun 04 01:28:17 PM PDT 24 15882554966 ps
T34 /workspace/coverage/default/28.sram_ctrl_ram_cfg.2508748150 Jun 04 01:23:59 PM PDT 24 Jun 04 01:24:01 PM PDT 24 33353644 ps
T74 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3067632010 Jun 04 01:27:43 PM PDT 24 Jun 04 01:46:38 PM PDT 24 4068784708 ps
T75 /workspace/coverage/default/49.sram_ctrl_ram_cfg.2007544034 Jun 04 01:27:58 PM PDT 24 Jun 04 01:27:59 PM PDT 24 52467403 ps
T76 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3497625206 Jun 04 01:26:28 PM PDT 24 Jun 04 01:31:00 PM PDT 24 12508616643 ps
T77 /workspace/coverage/default/20.sram_ctrl_mem_walk.3543659062 Jun 04 01:22:42 PM PDT 24 Jun 04 01:22:49 PM PDT 24 683904348 ps
T78 /workspace/coverage/default/36.sram_ctrl_alert_test.10508340 Jun 04 01:25:38 PM PDT 24 Jun 04 01:25:39 PM PDT 24 18343318 ps
T79 /workspace/coverage/default/27.sram_ctrl_alert_test.3025422755 Jun 04 01:23:53 PM PDT 24 Jun 04 01:23:55 PM PDT 24 15314383 ps
T9 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2074065328 Jun 04 01:21:02 PM PDT 24 Jun 04 01:21:08 PM PDT 24 269683252 ps
T80 /workspace/coverage/default/41.sram_ctrl_partial_access.781038771 Jun 04 01:26:27 PM PDT 24 Jun 04 01:26:35 PM PDT 24 1251520557 ps
T81 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1999161197 Jun 04 01:22:51 PM PDT 24 Jun 04 01:28:25 PM PDT 24 21408949938 ps
T82 /workspace/coverage/default/15.sram_ctrl_max_throughput.1057648517 Jun 04 01:21:53 PM PDT 24 Jun 04 01:23:53 PM PDT 24 428893269 ps
T170 /workspace/coverage/default/9.sram_ctrl_ram_cfg.2696069782 Jun 04 01:21:15 PM PDT 24 Jun 04 01:21:16 PM PDT 24 52123154 ps
T162 /workspace/coverage/default/15.sram_ctrl_smoke.1880853035 Jun 04 01:21:52 PM PDT 24 Jun 04 01:22:10 PM PDT 24 892319727 ps
T85 /workspace/coverage/default/28.sram_ctrl_executable.2062081626 Jun 04 01:23:59 PM PDT 24 Jun 04 01:34:44 PM PDT 24 28203684606 ps
T50 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2723338342 Jun 04 01:27:38 PM PDT 24 Jun 04 01:27:42 PM PDT 24 885720911 ps
T104 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2824435052 Jun 04 01:25:19 PM PDT 24 Jun 04 01:25:23 PM PDT 24 296188289 ps
T72 /workspace/coverage/default/47.sram_ctrl_regwen.3432723437 Jun 04 01:27:36 PM PDT 24 Jun 04 01:30:10 PM PDT 24 908101446 ps
T171 /workspace/coverage/default/12.sram_ctrl_executable.3715365461 Jun 04 01:21:37 PM PDT 24 Jun 04 01:27:16 PM PDT 24 3860065663 ps
T86 /workspace/coverage/default/31.sram_ctrl_multiple_keys.769223238 Jun 04 01:24:38 PM PDT 24 Jun 04 01:39:36 PM PDT 24 9997948731 ps
T132 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1249736762 Jun 04 01:25:46 PM PDT 24 Jun 04 01:34:31 PM PDT 24 19039304147 ps
T105 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2652474330 Jun 04 01:24:00 PM PDT 24 Jun 04 01:24:06 PM PDT 24 934016365 ps
T172 /workspace/coverage/default/46.sram_ctrl_smoke.2984044868 Jun 04 01:27:20 PM PDT 24 Jun 04 01:28:26 PM PDT 24 222888180 ps
T164 /workspace/coverage/default/15.sram_ctrl_ram_cfg.1195812605 Jun 04 01:22:01 PM PDT 24 Jun 04 01:22:02 PM PDT 24 242396223 ps
T106 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.4074520807 Jun 04 01:25:04 PM PDT 24 Jun 04 01:25:08 PM PDT 24 604174802 ps
T173 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4059936419 Jun 04 01:22:04 PM PDT 24 Jun 04 01:24:20 PM PDT 24 681367512 ps
T174 /workspace/coverage/default/34.sram_ctrl_alert_test.1466287659 Jun 04 01:25:20 PM PDT 24 Jun 04 01:25:22 PM PDT 24 39394149 ps
T175 /workspace/coverage/default/11.sram_ctrl_partial_access.915263349 Jun 04 01:21:26 PM PDT 24 Jun 04 01:21:45 PM PDT 24 1030972818 ps
T176 /workspace/coverage/default/18.sram_ctrl_smoke.2399932352 Jun 04 01:22:14 PM PDT 24 Jun 04 01:23:25 PM PDT 24 523691979 ps
T177 /workspace/coverage/default/19.sram_ctrl_alert_test.1050928180 Jun 04 01:22:34 PM PDT 24 Jun 04 01:22:35 PM PDT 24 34425192 ps
T107 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1619615147 Jun 04 01:21:39 PM PDT 24 Jun 04 01:21:43 PM PDT 24 233445260 ps
T178 /workspace/coverage/default/48.sram_ctrl_max_throughput.769240766 Jun 04 01:27:45 PM PDT 24 Jun 04 01:29:59 PM PDT 24 173360546 ps
T179 /workspace/coverage/default/10.sram_ctrl_mem_walk.1249787426 Jun 04 01:21:23 PM PDT 24 Jun 04 01:21:29 PM PDT 24 179591781 ps
T180 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3650660633 Jun 04 01:25:11 PM PDT 24 Jun 04 01:25:51 PM PDT 24 115357673 ps
T181 /workspace/coverage/default/0.sram_ctrl_bijection.1653524893 Jun 04 01:20:30 PM PDT 24 Jun 04 01:21:05 PM PDT 24 1231377690 ps
T182 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2389561458 Jun 04 01:20:54 PM PDT 24 Jun 04 01:25:53 PM PDT 24 11416961838 ps
T183 /workspace/coverage/default/40.sram_ctrl_smoke.1402428530 Jun 04 01:26:14 PM PDT 24 Jun 04 01:26:17 PM PDT 24 63679910 ps
T184 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3854175019 Jun 04 01:21:45 PM PDT 24 Jun 04 01:22:09 PM PDT 24 458197990 ps
T155 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.54443487 Jun 04 01:22:58 PM PDT 24 Jun 04 01:31:49 PM PDT 24 89917741945 ps
T185 /workspace/coverage/default/40.sram_ctrl_partial_access.705520820 Jun 04 01:26:21 PM PDT 24 Jun 04 01:26:35 PM PDT 24 1394459646 ps
T48 /workspace/coverage/default/10.sram_ctrl_executable.1368703049 Jun 04 01:21:22 PM PDT 24 Jun 04 01:34:53 PM PDT 24 45082012568 ps
T186 /workspace/coverage/default/16.sram_ctrl_bijection.4163226957 Jun 04 01:21:58 PM PDT 24 Jun 04 01:22:44 PM PDT 24 2949375337 ps
T187 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1556154632 Jun 04 01:20:46 PM PDT 24 Jun 04 01:25:34 PM PDT 24 34293778275 ps
T188 /workspace/coverage/default/13.sram_ctrl_max_throughput.753766479 Jun 04 01:21:43 PM PDT 24 Jun 04 01:21:50 PM PDT 24 246480331 ps
T27 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2708044099 Jun 04 01:21:26 PM PDT 24 Jun 04 01:21:32 PM PDT 24 4232398457 ps
T189 /workspace/coverage/default/3.sram_ctrl_max_throughput.1747763602 Jun 04 01:20:54 PM PDT 24 Jun 04 01:22:52 PM PDT 24 522087259 ps
T190 /workspace/coverage/default/17.sram_ctrl_max_throughput.1580952494 Jun 04 01:22:12 PM PDT 24 Jun 04 01:22:19 PM PDT 24 50891588 ps
T191 /workspace/coverage/default/20.sram_ctrl_alert_test.2705330669 Jun 04 01:22:52 PM PDT 24 Jun 04 01:22:54 PM PDT 24 21669323 ps
T192 /workspace/coverage/default/1.sram_ctrl_bijection.1518932647 Jun 04 01:20:35 PM PDT 24 Jun 04 01:21:49 PM PDT 24 12155793757 ps
T193 /workspace/coverage/default/31.sram_ctrl_max_throughput.167207422 Jun 04 01:24:34 PM PDT 24 Jun 04 01:26:20 PM PDT 24 125458666 ps
T194 /workspace/coverage/default/30.sram_ctrl_smoke.1591364770 Jun 04 01:24:13 PM PDT 24 Jun 04 01:24:49 PM PDT 24 459884390 ps
T195 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1744541313 Jun 04 01:22:26 PM PDT 24 Jun 04 01:26:32 PM PDT 24 7501697305 ps
T196 /workspace/coverage/default/46.sram_ctrl_mem_walk.2984535319 Jun 04 01:27:30 PM PDT 24 Jun 04 01:27:42 PM PDT 24 804680204 ps
T197 /workspace/coverage/default/30.sram_ctrl_partial_access.2149610948 Jun 04 01:24:21 PM PDT 24 Jun 04 01:24:45 PM PDT 24 4613519185 ps
T198 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2715733092 Jun 04 01:27:44 PM PDT 24 Jun 04 01:31:54 PM PDT 24 24190599890 ps
T49 /workspace/coverage/default/1.sram_ctrl_regwen.3460447627 Jun 04 01:20:48 PM PDT 24 Jun 04 01:29:45 PM PDT 24 19070841593 ps
T199 /workspace/coverage/default/45.sram_ctrl_mem_walk.3588266341 Jun 04 01:27:12 PM PDT 24 Jun 04 01:27:20 PM PDT 24 6601570784 ps
T108 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3025136687 Jun 04 01:20:56 PM PDT 24 Jun 04 01:21:03 PM PDT 24 333242596 ps
T25 /workspace/coverage/default/49.sram_ctrl_lc_escalation.265804288 Jun 04 01:28:01 PM PDT 24 Jun 04 01:28:09 PM PDT 24 1365264839 ps
T200 /workspace/coverage/default/5.sram_ctrl_bijection.548179332 Jun 04 01:20:55 PM PDT 24 Jun 04 01:21:11 PM PDT 24 981142568 ps
T201 /workspace/coverage/default/39.sram_ctrl_alert_test.1333779883 Jun 04 01:26:14 PM PDT 24 Jun 04 01:26:15 PM PDT 24 17274701 ps
T133 /workspace/coverage/default/45.sram_ctrl_executable.2834932948 Jun 04 01:27:15 PM PDT 24 Jun 04 01:37:39 PM PDT 24 2233752227 ps
T202 /workspace/coverage/default/26.sram_ctrl_bijection.2956971554 Jun 04 01:23:38 PM PDT 24 Jun 04 01:24:22 PM PDT 24 2769752700 ps
T203 /workspace/coverage/default/4.sram_ctrl_alert_test.3636279217 Jun 04 01:20:55 PM PDT 24 Jun 04 01:20:57 PM PDT 24 45518659 ps
T204 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1032260460 Jun 04 01:20:35 PM PDT 24 Jun 04 01:21:01 PM PDT 24 338877951 ps
T205 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1394698988 Jun 04 01:21:03 PM PDT 24 Jun 04 01:21:05 PM PDT 24 30536823 ps
T206 /workspace/coverage/default/37.sram_ctrl_executable.396269911 Jun 04 01:25:46 PM PDT 24 Jun 04 01:34:17 PM PDT 24 18764656887 ps
T207 /workspace/coverage/default/29.sram_ctrl_alert_test.1462153982 Jun 04 01:24:11 PM PDT 24 Jun 04 01:24:13 PM PDT 24 27192941 ps
T208 /workspace/coverage/default/45.sram_ctrl_alert_test.3107338630 Jun 04 01:27:20 PM PDT 24 Jun 04 01:27:22 PM PDT 24 45659405 ps
T209 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1084934468 Jun 04 01:24:21 PM PDT 24 Jun 04 01:24:24 PM PDT 24 311608818 ps
T210 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2837208146 Jun 04 01:22:12 PM PDT 24 Jun 04 01:28:49 PM PDT 24 16153767981 ps
T211 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1406083228 Jun 04 01:21:24 PM PDT 24 Jun 04 01:25:28 PM PDT 24 5721776408 ps
T212 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2914694162 Jun 04 01:26:28 PM PDT 24 Jun 04 01:31:20 PM PDT 24 5377057261 ps
T213 /workspace/coverage/default/9.sram_ctrl_bijection.2954431144 Jun 04 01:21:15 PM PDT 24 Jun 04 01:22:55 PM PDT 24 21664795289 ps
T87 /workspace/coverage/default/29.sram_ctrl_regwen.3002273128 Jun 04 01:24:06 PM PDT 24 Jun 04 01:37:01 PM PDT 24 5862884397 ps
T214 /workspace/coverage/default/38.sram_ctrl_lc_escalation.1589035114 Jun 04 01:26:02 PM PDT 24 Jun 04 01:26:10 PM PDT 24 2474374958 ps
T215 /workspace/coverage/default/28.sram_ctrl_multiple_keys.944532735 Jun 04 01:23:52 PM PDT 24 Jun 04 01:38:12 PM PDT 24 23497718364 ps
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T218 /workspace/coverage/default/5.sram_ctrl_max_throughput.4289185481 Jun 04 01:20:55 PM PDT 24 Jun 04 01:21:49 PM PDT 24 484387091 ps
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T219 /workspace/coverage/default/49.sram_ctrl_bijection.2507851782 Jun 04 01:27:59 PM PDT 24 Jun 04 01:28:22 PM PDT 24 5176544400 ps
T220 /workspace/coverage/default/5.sram_ctrl_partial_access.1134360035 Jun 04 01:20:59 PM PDT 24 Jun 04 01:21:16 PM PDT 24 888901851 ps
T221 /workspace/coverage/default/44.sram_ctrl_max_throughput.2222908685 Jun 04 01:27:07 PM PDT 24 Jun 04 01:27:18 PM PDT 24 134147998 ps
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T224 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.336347870 Jun 04 01:27:19 PM PDT 24 Jun 04 01:29:08 PM PDT 24 150934043 ps
T225 /workspace/coverage/default/4.sram_ctrl_bijection.3841678332 Jun 04 01:20:54 PM PDT 24 Jun 04 01:22:24 PM PDT 24 3623150617 ps
T226 /workspace/coverage/default/41.sram_ctrl_mem_walk.1251128127 Jun 04 01:26:36 PM PDT 24 Jun 04 01:26:45 PM PDT 24 448019087 ps
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T109 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2359976312 Jun 04 01:21:01 PM PDT 24 Jun 04 01:21:08 PM PDT 24 357553066 ps
T228 /workspace/coverage/default/43.sram_ctrl_executable.2394311149 Jun 04 01:26:58 PM PDT 24 Jun 04 01:33:06 PM PDT 24 6186674918 ps
T229 /workspace/coverage/default/33.sram_ctrl_partial_access.3208967719 Jun 04 01:25:00 PM PDT 24 Jun 04 01:25:19 PM PDT 24 568758294 ps
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T230 /workspace/coverage/default/4.sram_ctrl_mem_walk.3289678461 Jun 04 01:20:56 PM PDT 24 Jun 04 01:21:03 PM PDT 24 241846124 ps
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T153 /workspace/coverage/default/46.sram_ctrl_regwen.931762721 Jun 04 01:27:22 PM PDT 24 Jun 04 01:38:31 PM PDT 24 36796650159 ps
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T231 /workspace/coverage/default/8.sram_ctrl_executable.862864248 Jun 04 01:21:08 PM PDT 24 Jun 04 01:25:58 PM PDT 24 1434439137 ps
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T233 /workspace/coverage/default/24.sram_ctrl_alert_test.1212448365 Jun 04 01:23:24 PM PDT 24 Jun 04 01:23:26 PM PDT 24 40520795 ps
T234 /workspace/coverage/default/21.sram_ctrl_smoke.3835320775 Jun 04 01:22:51 PM PDT 24 Jun 04 01:22:57 PM PDT 24 91693979 ps
T235 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1031320604 Jun 04 01:20:55 PM PDT 24 Jun 04 01:21:15 PM PDT 24 151998181 ps
T236 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4120695850 Jun 04 01:21:07 PM PDT 24 Jun 04 01:21:10 PM PDT 24 166679670 ps
T237 /workspace/coverage/default/25.sram_ctrl_mem_walk.1118062569 Jun 04 01:23:33 PM PDT 24 Jun 04 01:23:45 PM PDT 24 971026213 ps
T238 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.591394465 Jun 04 01:23:05 PM PDT 24 Jun 04 01:24:13 PM PDT 24 310125692 ps
T239 /workspace/coverage/default/47.sram_ctrl_partial_access.1431156972 Jun 04 01:27:27 PM PDT 24 Jun 04 01:27:33 PM PDT 24 995576781 ps
T110 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4138330937 Jun 04 01:22:06 PM PDT 24 Jun 04 01:22:10 PM PDT 24 391242118 ps
T156 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3570713620 Jun 04 01:21:42 PM PDT 24 Jun 04 01:29:53 PM PDT 24 31214798237 ps
T111 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1276285959 Jun 04 01:24:06 PM PDT 24 Jun 04 01:24:12 PM PDT 24 481693185 ps
T240 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4144600491 Jun 04 01:23:04 PM PDT 24 Jun 04 01:28:38 PM PDT 24 12366528480 ps
T241 /workspace/coverage/default/41.sram_ctrl_lc_escalation.3755951768 Jun 04 01:26:28 PM PDT 24 Jun 04 01:26:36 PM PDT 24 518044823 ps
T242 /workspace/coverage/default/18.sram_ctrl_lc_escalation.1564348790 Jun 04 01:22:20 PM PDT 24 Jun 04 01:22:31 PM PDT 24 924081877 ps
T243 /workspace/coverage/default/24.sram_ctrl_regwen.123403850 Jun 04 01:23:19 PM PDT 24 Jun 04 01:36:47 PM PDT 24 46514244643 ps
T244 /workspace/coverage/default/25.sram_ctrl_executable.1660399072 Jun 04 01:23:33 PM PDT 24 Jun 04 01:28:58 PM PDT 24 5550587223 ps
T120 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3064867040 Jun 04 01:20:47 PM PDT 24 Jun 04 01:20:53 PM PDT 24 120489682 ps
T245 /workspace/coverage/default/13.sram_ctrl_partial_access.1490689461 Jun 04 01:21:43 PM PDT 24 Jun 04 01:22:57 PM PDT 24 266666729 ps
T246 /workspace/coverage/default/19.sram_ctrl_executable.69866932 Jun 04 01:22:28 PM PDT 24 Jun 04 01:44:01 PM PDT 24 8607104726 ps
T247 /workspace/coverage/default/34.sram_ctrl_smoke.1571343896 Jun 04 01:25:04 PM PDT 24 Jun 04 01:26:41 PM PDT 24 1022386606 ps
T248 /workspace/coverage/default/41.sram_ctrl_max_throughput.1692511561 Jun 04 01:26:27 PM PDT 24 Jun 04 01:27:53 PM PDT 24 113073856 ps
T249 /workspace/coverage/default/13.sram_ctrl_multiple_keys.2199473656 Jun 04 01:21:44 PM PDT 24 Jun 04 01:37:02 PM PDT 24 11446079634 ps
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T252 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.455564798 Jun 04 01:27:58 PM PDT 24 Jun 04 01:35:51 PM PDT 24 17023421629 ps
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T254 /workspace/coverage/default/29.sram_ctrl_ram_cfg.1449683493 Jun 04 01:24:06 PM PDT 24 Jun 04 01:24:08 PM PDT 24 213384462 ps
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T257 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1949969435 Jun 04 01:27:37 PM PDT 24 Jun 04 01:27:41 PM PDT 24 222026429 ps
T258 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3246313138 Jun 04 01:21:18 PM PDT 24 Jun 04 01:21:34 PM PDT 24 77862134 ps
T160 /workspace/coverage/default/38.sram_ctrl_partial_access.1801737912 Jun 04 01:25:55 PM PDT 24 Jun 04 01:26:36 PM PDT 24 780334905 ps
T259 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1050444766 Jun 04 01:20:36 PM PDT 24 Jun 04 01:24:55 PM PDT 24 8019078923 ps
T157 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3874678291 Jun 04 01:26:14 PM PDT 24 Jun 04 01:26:21 PM PDT 24 330964975 ps
T260 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.649917960 Jun 04 01:21:50 PM PDT 24 Jun 04 01:21:52 PM PDT 24 79381498 ps
T261 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1671719462 Jun 04 01:21:23 PM PDT 24 Jun 04 01:26:26 PM PDT 24 15813281166 ps
T262 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.62663008 Jun 04 01:24:50 PM PDT 24 Jun 04 01:26:39 PM PDT 24 524052316 ps
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T265 /workspace/coverage/default/24.sram_ctrl_partial_access.415207409 Jun 04 01:23:17 PM PDT 24 Jun 04 01:23:19 PM PDT 24 104994426 ps
T159 /workspace/coverage/default/25.sram_ctrl_multiple_keys.2340606648 Jun 04 01:23:27 PM PDT 24 Jun 04 01:36:21 PM PDT 24 27370097591 ps
T266 /workspace/coverage/default/45.sram_ctrl_bijection.3834712257 Jun 04 01:27:19 PM PDT 24 Jun 04 01:28:14 PM PDT 24 1050556588 ps
T267 /workspace/coverage/default/9.sram_ctrl_partial_access.3034170004 Jun 04 01:21:14 PM PDT 24 Jun 04 01:22:06 PM PDT 24 2560735100 ps
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T269 /workspace/coverage/default/48.sram_ctrl_regwen.1269606597 Jun 04 01:27:43 PM PDT 24 Jun 04 01:39:19 PM PDT 24 6639268088 ps
T270 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2496764690 Jun 04 01:22:57 PM PDT 24 Jun 04 01:27:20 PM PDT 24 4044025017 ps
T271 /workspace/coverage/default/40.sram_ctrl_max_throughput.4149517346 Jun 04 01:26:21 PM PDT 24 Jun 04 01:26:29 PM PDT 24 109395148 ps
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T37 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1990428012 Jun 04 01:22:33 PM PDT 24 Jun 04 01:22:37 PM PDT 24 652015813 ps
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T40 /workspace/coverage/default/2.sram_ctrl_partial_access.999929970 Jun 04 01:20:47 PM PDT 24 Jun 04 01:21:05 PM PDT 24 1002021921 ps
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T43 /workspace/coverage/default/28.sram_ctrl_partial_access.2217305198 Jun 04 01:23:54 PM PDT 24 Jun 04 01:24:04 PM PDT 24 535552307 ps
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T273 /workspace/coverage/default/39.sram_ctrl_partial_access.1080442645 Jun 04 01:26:05 PM PDT 24 Jun 04 01:26:23 PM PDT 24 1588676758 ps
T274 /workspace/coverage/default/26.sram_ctrl_max_throughput.907389103 Jun 04 01:23:38 PM PDT 24 Jun 04 01:24:31 PM PDT 24 427980435 ps
T275 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1764366895 Jun 04 01:26:20 PM PDT 24 Jun 04 01:26:21 PM PDT 24 28550452 ps
T276 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3114621604 Jun 04 01:25:25 PM PDT 24 Jun 04 01:25:31 PM PDT 24 242083721 ps
T277 /workspace/coverage/default/29.sram_ctrl_max_throughput.2381268972 Jun 04 01:24:06 PM PDT 24 Jun 04 01:26:32 PM PDT 24 133815071 ps
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T279 /workspace/coverage/default/18.sram_ctrl_max_throughput.3865295100 Jun 04 01:22:18 PM PDT 24 Jun 04 01:23:09 PM PDT 24 183810013 ps
T280 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2362324294 Jun 04 01:22:02 PM PDT 24 Jun 04 01:27:17 PM PDT 24 5150692772 ps
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T283 /workspace/coverage/default/37.sram_ctrl_alert_test.4265202088 Jun 04 01:25:53 PM PDT 24 Jun 04 01:25:54 PM PDT 24 42757714 ps
T284 /workspace/coverage/default/42.sram_ctrl_executable.2058793517 Jun 04 01:26:41 PM PDT 24 Jun 04 01:28:25 PM PDT 24 483588183 ps
T285 /workspace/coverage/default/1.sram_ctrl_lc_escalation.3231284676 Jun 04 01:20:37 PM PDT 24 Jun 04 01:20:45 PM PDT 24 584687971 ps
T286 /workspace/coverage/default/7.sram_ctrl_multiple_keys.340311080 Jun 04 01:21:00 PM PDT 24 Jun 04 01:36:26 PM PDT 24 12354619435 ps
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T288 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4062104300 Jun 04 01:20:55 PM PDT 24 Jun 04 01:22:20 PM PDT 24 512929614 ps
T289 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3869997195 Jun 04 01:27:06 PM PDT 24 Jun 04 01:28:29 PM PDT 24 496801089 ps
T290 /workspace/coverage/default/41.sram_ctrl_bijection.3886665316 Jun 04 01:26:21 PM PDT 24 Jun 04 01:27:14 PM PDT 24 830251102 ps
T30 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2719587810 Jun 04 01:22:51 PM PDT 24 Jun 04 01:23:09 PM PDT 24 757622130 ps
T291 /workspace/coverage/default/31.sram_ctrl_ram_cfg.140279232 Jun 04 01:24:35 PM PDT 24 Jun 04 01:24:36 PM PDT 24 47030395 ps
T292 /workspace/coverage/default/49.sram_ctrl_max_throughput.741455401 Jun 04 01:27:59 PM PDT 24 Jun 04 01:29:31 PM PDT 24 440289422 ps
T293 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2251478959 Jun 04 01:23:39 PM PDT 24 Jun 04 01:23:42 PM PDT 24 41933844 ps
T294 /workspace/coverage/default/27.sram_ctrl_multiple_keys.1156470359 Jun 04 01:23:46 PM PDT 24 Jun 04 01:46:02 PM PDT 24 10149449756 ps
T295 /workspace/coverage/default/27.sram_ctrl_lc_escalation.114238043 Jun 04 01:23:45 PM PDT 24 Jun 04 01:23:51 PM PDT 24 414788527 ps
T296 /workspace/coverage/default/36.sram_ctrl_mem_walk.2944948844 Jun 04 01:25:39 PM PDT 24 Jun 04 01:25:44 PM PDT 24 289278777 ps
T20 /workspace/coverage/default/4.sram_ctrl_sec_cm.2146634944 Jun 04 01:20:54 PM PDT 24 Jun 04 01:20:58 PM PDT 24 211210122 ps
T297 /workspace/coverage/default/29.sram_ctrl_partial_access.1357286658 Jun 04 01:24:06 PM PDT 24 Jun 04 01:24:25 PM PDT 24 376054596 ps
T141 /workspace/coverage/default/20.sram_ctrl_lc_escalation.724682611 Jun 04 01:22:43 PM PDT 24 Jun 04 01:22:46 PM PDT 24 229364886 ps
T298 /workspace/coverage/default/46.sram_ctrl_partial_access.3336974774 Jun 04 01:27:21 PM PDT 24 Jun 04 01:27:42 PM PDT 24 3914904543 ps
T299 /workspace/coverage/default/38.sram_ctrl_mem_walk.214430213 Jun 04 01:25:59 PM PDT 24 Jun 04 01:26:05 PM PDT 24 180295203 ps
T300 /workspace/coverage/default/32.sram_ctrl_smoke.2016297571 Jun 04 01:24:42 PM PDT 24 Jun 04 01:24:51 PM PDT 24 163399832 ps
T301 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3807918960 Jun 04 01:21:45 PM PDT 24 Jun 04 01:25:41 PM PDT 24 2809266423 ps
T302 /workspace/coverage/default/45.sram_ctrl_multiple_keys.944484992 Jun 04 01:27:13 PM PDT 24 Jun 04 01:27:45 PM PDT 24 1784442387 ps
T303 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.624855734 Jun 04 01:22:27 PM PDT 24 Jun 04 01:29:22 PM PDT 24 60279024683 ps
T304 /workspace/coverage/default/49.sram_ctrl_smoke.1122886538 Jun 04 01:27:50 PM PDT 24 Jun 04 01:28:03 PM PDT 24 491997837 ps
T305 /workspace/coverage/default/35.sram_ctrl_executable.2816053126 Jun 04 01:25:26 PM PDT 24 Jun 04 01:34:22 PM PDT 24 1881138176 ps
T306 /workspace/coverage/default/17.sram_ctrl_mem_walk.2531031428 Jun 04 01:22:13 PM PDT 24 Jun 04 01:22:18 PM PDT 24 74334592 ps
T307 /workspace/coverage/default/19.sram_ctrl_max_throughput.4050633773 Jun 04 01:22:29 PM PDT 24 Jun 04 01:22:53 PM PDT 24 366866708 ps
T308 /workspace/coverage/default/49.sram_ctrl_executable.3111321201 Jun 04 01:27:59 PM PDT 24 Jun 04 01:43:45 PM PDT 24 11396258154 ps
T309 /workspace/coverage/default/26.sram_ctrl_alert_test.22240029 Jun 04 01:23:46 PM PDT 24 Jun 04 01:23:47 PM PDT 24 16947507 ps
T310 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1289842675 Jun 04 01:23:18 PM PDT 24 Jun 04 01:23:24 PM PDT 24 305467025 ps
T311 /workspace/coverage/default/31.sram_ctrl_smoke.2937902448 Jun 04 01:24:38 PM PDT 24 Jun 04 01:25:24 PM PDT 24 1393351850 ps
T312 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.887496151 Jun 04 01:20:57 PM PDT 24 Jun 04 01:21:03 PM PDT 24 204206378 ps
T313 /workspace/coverage/default/46.sram_ctrl_bijection.2644578690 Jun 04 01:27:22 PM PDT 24 Jun 04 01:28:18 PM PDT 24 3072448690 ps
T314 /workspace/coverage/default/7.sram_ctrl_max_throughput.2513061456 Jun 04 01:21:00 PM PDT 24 Jun 04 01:22:59 PM PDT 24 143840785 ps
T315 /workspace/coverage/default/39.sram_ctrl_bijection.2629945246 Jun 04 01:26:06 PM PDT 24 Jun 04 01:26:40 PM PDT 24 868232088 ps
T316 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2921413771 Jun 04 01:25:47 PM PDT 24 Jun 04 01:31:00 PM PDT 24 18761983897 ps
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