Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	24991728	1			T1	18818		T3	22528		T4	93070
triple_byte_access	2123664	1			T1	17190		T4	1892		T5	965
halfword_access	3186952	1			T1	25718		T4	2765		T5	1443
byte_access	4254619	1			T1	34086		T4	3848		T5	2033
zero_access	1073000	1			T1	8550		T4	985		T5	489

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17764867

1

T1

52063

T3

11264

T4

51269

auto[1]

17865096

1

T1

52299

T3

11264

T4

51291

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	12453427	1			T1	9366		T3	11264		T4	46513
auto[0]	triple_byte_access	1058124	1			T1	8458		T4	938		T5	512
auto[0]	halfword_access	1589307	1			T1	12910		T4	1365		T5	741
auto[0]	byte_access	2124649	1			T1	17044		T4	1943		T5	1010
auto[0]	zero_access	539360	1			T1	4285		T4	510		T5	243
auto[1]	word_access	12538301	1			T1	9452		T3	11264		T4	46557
auto[1]	triple_byte_access	1065540	1			T1	8732		T4	954		T5	453
auto[1]	halfword_access	1597645	1			T1	12808		T4	1400		T5	702
auto[1]	byte_access	2129970	1			T1	17042		T4	1905		T5	1023
auto[1]	zero_access	533640	1			T1	4265		T4	475		T5	246