Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148668268	1			T1	455730		T2	106735		T3	12284
instr_valid_dis	118299287	1			T1	455730		T2	752010		T3	12284
instr_en	22273027	1			T2	315340		T11	246126		T12	249338

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9941600	1			T2	70410		T11	155824		T12	72410
sram_ifetch_valid_disable	118006387	1			T1	455730		T2	405492		T3	12284
sram_ifetch_enable	20720281	1			T2	591448		T11	27796		T12	99044

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148668268	1			T1	455730		T2	106735		T3	12284
hw_debug_en_valid_off	117428915	1			T1	455730		T2	824800		T3	12284
hw_debug_en_on	20658981	1			T2	210352		T11	253336		T12	159224

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118006387	1			T1	455730		T2	405492		T3	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	105119209	1			T1	455730		T2	371890		T3	12284
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9483904	1			T2	33602		T11	121902		T12	77884
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4087586	1			T2	61684		T12	62828		T60	28114
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1652786	1			T69	15238		T21	53748		T72	31506
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1745410	1			T2	61684		T12	62828		T60	28114
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3600564	1			T2	8726		T11	138704		T50	59860
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1455812	1			T2	8726		T50	8226		T69	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1691400	1			T11	114208		T50	11728		T69	29202
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9251756	1			T2	3076		T11	112478		T12	92394
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4738951	1			T12	72394		T26	34711		T69	64752
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3412127	1			T2	3076		T11	72498		T12	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8124069	1			T2	220054		T11	10016		T12	99044
lc_exec_en	7806661	1			T2	198550		T11	2154		T12	66830
valid_exec_dis	113915847	1			T1	455730		T2	753810		T3	12284
invalid_exec_dis	30661881	1			T2	661858		T11	183620		T12	171454