Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44911792	1			T1	41423		T2	283564		T3	6142
triple_byte_access	2584000	1			T1	37283		T2	5615		T4	245
halfword_access	3876274	1			T1	55940		T2	8470		T4	392
byte_access	5178264	1			T1	74518		T2	11530		T4	807
zero_access	1302665	1			T1	18701		T2	2855		T4	437

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28867408

1

T1

113748

T2

156075

T3

2048

auto[1]

28985587

1

T1

114117

T2

155959

T3

4094

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22403028	1			T1	20726		T2	141756		T3	2048
auto[0]	triple_byte_access	1287499	1			T1	18721		T2	2820		T4	28
auto[0]	halfword_access	1932810	1			T1	27789		T2	4245		T4	114
auto[0]	byte_access	2588175	1			T1	37100		T2	5812		T4	391
auto[0]	zero_access	655896	1			T1	9412		T2	1442		T4	346
auto[1]	word_access	22508764	1			T1	20697		T2	141808		T3	4094
auto[1]	triple_byte_access	1296501	1			T1	18562		T2	2795		T4	217
auto[1]	halfword_access	1943464	1			T1	28151		T2	4225		T4	278
auto[1]	byte_access	2590089	1			T1	37418		T2	5718		T4	416
auto[1]	zero_access	646769	1			T1	9289		T2	1413		T4	91