Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13896591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61972639

1

T2

186608

T3

23813

T4

4073

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37817520	1			T2	102525		T3	13121		T4	2240
values[0x0]	17635243	1			T2	49515		T3	6240		T4	1060
values[0x1]	20416467	1			T2	53200		T3	6871		T4	1169

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6923197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68946033

1

T2

195897

T3

25034

T4

4276

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	322427	1			T2	782		T3	85		T4	32
valid_sources[0x01]	329174	1			T2	766		T3	103		T6	2
valid_sources[0x02]	314729	1			T2	795		T3	127		T4	12
valid_sources[0x03]	318798	1			T2	801		T3	93		T4	17
valid_sources[0x04]	312212	1			T2	784		T3	125		T4	13
valid_sources[0x05]	282667	1			T2	725		T3	121		T6	3
valid_sources[0x06]	290876	1			T2	830		T3	96		T4	12
valid_sources[0x07]	254259	1			T2	848		T3	89		T4	31
valid_sources[0x08]	273424	1			T2	761		T3	115		T4	33
valid_sources[0x09]	341389	1			T2	803		T3	119		T4	100
valid_sources[0x0a]	279209	1			T2	793		T3	85		T4	54
valid_sources[0x0b]	254929	1			T2	841		T3	88		T4	10
valid_sources[0x0c]	271718	1			T2	795		T3	68		T4	11
valid_sources[0x0d]	285414	1			T2	858		T3	118		T4	15
valid_sources[0x0e]	266569	1			T2	786		T3	97		T4	36
valid_sources[0x0f]	304786	1			T2	792		T3	100		T4	22
valid_sources[0x10]	265531	1			T2	791		T3	116		T4	62
valid_sources[0x11]	290568	1			T2	823		T3	78		T6	1
valid_sources[0x12]	275094	1			T2	830		T3	111		T4	14
valid_sources[0x13]	269545	1			T2	793		T3	112		T4	37
valid_sources[0x14]	302593	1			T2	813		T3	109		T4	13
valid_sources[0x15]	255664	1			T2	761		T3	70		T4	16
valid_sources[0x16]	318243	1			T2	795		T3	109		T6	9
valid_sources[0x17]	263883	1			T2	818		T3	141		T4	14
valid_sources[0x18]	314943	1			T2	727		T3	141		T4	20
valid_sources[0x19]	260795	1			T2	821		T3	97		T4	20
valid_sources[0x1a]	294062	1			T2	768		T3	98		T11	27
valid_sources[0x1b]	279532	1			T2	819		T3	130		T4	13
valid_sources[0x1c]	289723	1			T2	800		T3	118		T4	5
valid_sources[0x1d]	280123	1			T2	817		T3	82		T4	10
valid_sources[0x1e]	295420	1			T2	778		T3	109		T4	23
valid_sources[0x1f]	356697	1			T2	773		T3	80		T4	13
valid_sources[0x20]	333399	1			T2	778		T3	115		T4	4
valid_sources[0x21]	371970	1			T2	803		T3	117		T4	15
valid_sources[0x22]	258546	1			T2	802		T3	130		T4	1
valid_sources[0x23]	308278	1			T2	823		T3	96		T4	11
valid_sources[0x24]	348772	1			T2	762		T3	140		T4	22
valid_sources[0x25]	387607	1			T2	854		T3	95		T4	17
valid_sources[0x26]	306481	1			T2	822		T3	91		T4	27
valid_sources[0x27]	292162	1			T2	729		T3	99		T4	10
valid_sources[0x28]	294495	1			T2	860		T3	86		T4	37
valid_sources[0x29]	284081	1			T2	817		T3	86		T4	30
valid_sources[0x2a]	282408	1			T2	772		T3	106		T4	23
valid_sources[0x2b]	314961	1			T2	816		T3	96		T4	20
valid_sources[0x2c]	295035	1			T2	829		T3	90		T4	12
valid_sources[0x2d]	293105	1			T2	772		T3	108		T4	4
valid_sources[0x2e]	271002	1			T2	841		T3	107		T4	20
valid_sources[0x2f]	313058	1			T2	839		T3	97		T11	11
valid_sources[0x30]	295201	1			T2	828		T3	83		T6	4
valid_sources[0x31]	291912	1			T2	805		T3	105		T4	9
valid_sources[0x32]	355207	1			T2	825		T3	100		T4	29
valid_sources[0x33]	304570	1			T2	782		T3	129		T4	3
valid_sources[0x34]	360860	1			T2	845		T3	124		T4	30
valid_sources[0x35]	313044	1			T2	824		T3	97		T4	7
valid_sources[0x36]	331879	1			T2	793		T3	81		T4	16
valid_sources[0x37]	273249	1			T2	815		T3	104		T4	10
valid_sources[0x38]	331168	1			T2	798		T3	124		T4	9
valid_sources[0x39]	282286	1			T2	766		T3	99		T4	8
valid_sources[0x3a]	284820	1			T2	834		T3	113		T6	2
valid_sources[0x3b]	288497	1			T2	779		T3	75		T4	13
valid_sources[0x3c]	276502	1			T2	834		T3	80		T4	19
valid_sources[0x3d]	291294	1			T2	816		T3	106		T4	3
valid_sources[0x3e]	336058	1			T2	807		T3	117		T4	24
valid_sources[0x3f]	308960	1			T2	841		T3	120		T4	15
valid_sources[0x40]	271976	1			T2	789		T3	129		T4	23
valid_sources[0x41]	268162	1			T2	770		T3	64		T4	20
valid_sources[0x42]	275374	1			T2	816		T3	83		T4	17
valid_sources[0x43]	336999	1			T2	766		T3	101		T6	8
valid_sources[0x44]	326432	1			T2	891		T3	114		T6	3
valid_sources[0x45]	330092	1			T2	821		T3	95		T4	8
valid_sources[0x46]	269251	1			T2	854		T3	112		T4	6
valid_sources[0x47]	304481	1			T2	790		T3	78		T4	1
valid_sources[0x48]	342398	1			T2	760		T3	85		T4	8
valid_sources[0x49]	412852	1			T2	776		T3	117		T4	9
valid_sources[0x4a]	260059	1			T2	827		T3	89		T4	13
valid_sources[0x4b]	288375	1			T2	805		T3	94		T4	7
valid_sources[0x4c]	318855	1			T2	732		T3	80		T4	18
valid_sources[0x4d]	290519	1			T2	793		T3	78		T4	1
valid_sources[0x4e]	278773	1			T2	805		T3	97		T4	14
valid_sources[0x4f]	302964	1			T2	852		T3	111		T4	3
valid_sources[0x50]	256587	1			T2	772		T3	118		T4	12
valid_sources[0x51]	276063	1			T2	814		T3	134		T4	57
valid_sources[0x52]	280274	1			T2	827		T3	123		T4	14
valid_sources[0x53]	321806	1			T2	800		T3	112		T4	6
valid_sources[0x54]	252261	1			T2	808		T3	121		T4	13
valid_sources[0x55]	284860	1			T2	801		T3	80		T4	5
valid_sources[0x56]	305346	1			T2	842		T3	86		T4	1
valid_sources[0x57]	359624	1			T2	847		T3	90		T4	9
valid_sources[0x58]	290249	1			T2	748		T3	96		T4	13
valid_sources[0x59]	248077	1			T2	872		T3	102		T4	12
valid_sources[0x5a]	293860	1			T2	817		T3	80		T4	32
valid_sources[0x5b]	275057	1			T2	822		T3	75		T4	31
valid_sources[0x5c]	300272	1			T2	799		T3	83		T4	2
valid_sources[0x5d]	301109	1			T2	772		T3	102		T4	19
valid_sources[0x5e]	293196	1			T2	854		T3	80		T11	4
valid_sources[0x5f]	357392	1			T2	750		T3	101		T4	2
valid_sources[0x60]	296515	1			T2	774		T3	88		T4	11
valid_sources[0x61]	400847	1			T2	830		T3	109		T4	38
valid_sources[0x62]	299656	1			T2	854		T3	94		T4	6
valid_sources[0x63]	350994	1			T2	831		T3	103		T4	5
valid_sources[0x64]	268426	1			T2	801		T3	111		T4	2
valid_sources[0x65]	350789	1			T2	764		T3	81		T4	18
valid_sources[0x66]	248359	1			T2	851		T3	134		T4	41
valid_sources[0x67]	296608	1			T2	794		T3	103		T4	10
valid_sources[0x68]	263580	1			T2	761		T3	108		T4	12
valid_sources[0x69]	268769	1			T2	872		T3	104		T4	1
valid_sources[0x6a]	323301	1			T2	795		T3	70		T11	8
valid_sources[0x6b]	264820	1			T2	833		T3	110		T4	5
valid_sources[0x6c]	282544	1			T2	785		T3	102		T4	52
valid_sources[0x6d]	264341	1			T2	776		T3	116		T4	49
valid_sources[0x6e]	350213	1			T2	778		T3	98		T4	19
valid_sources[0x6f]	278984	1			T2	776		T3	100		T4	30
valid_sources[0x70]	257127	1			T2	807		T3	93		T4	18
valid_sources[0x71]	301364	1			T2	798		T3	131		T4	66
valid_sources[0x72]	390542	1			T2	853		T3	108		T4	5
valid_sources[0x73]	286677	1			T2	847		T3	71		T4	15
valid_sources[0x74]	317387	1			T2	738		T3	105		T4	22
valid_sources[0x75]	248774	1			T2	799		T3	111		T11	16
valid_sources[0x76]	292961	1			T2	812		T3	100		T4	34
valid_sources[0x77]	303576	1			T2	837		T3	108		T4	30
valid_sources[0x78]	296299	1			T2	772		T3	91		T4	6
valid_sources[0x79]	302909	1			T2	738		T3	112		T4	4
valid_sources[0x7a]	260810	1			T2	875		T3	96		T4	48
valid_sources[0x7b]	392062	1			T2	740		T3	108		T4	8
valid_sources[0x7c]	277503	1			T2	765		T3	103		T4	4
valid_sources[0x7d]	264327	1			T2	769		T3	104		T4	8
valid_sources[0x7e]	283383	1			T2	824		T3	124		T6	3
valid_sources[0x7f]	257267	1			T2	784		T3	106		T4	1
valid_sources[0x80]	285461	1			T2	873		T3	96		T4	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30874539

1

T2

93301

T3

11861

T4

2040

values[0x0]

all_enables

biggest_size

15548721

1

T2

46670

T3

5881

T4

1010

values[0x1]

all_enables

biggest_size

15549379

1

T2

46637

T3

6071

T4

1023

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148080

1

T1

9

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52969	1			T7	85		T8	15		T14	30
values[0x0]	63821	1			T1	10		T2	1		T4	1
values[0x1]	68356	1			T1	9		T2	6		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157147

1

T1

11

T2

3

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1070	1			T14	2		T28	6		T22	17
valid_sources[0x01]	881	1			T37	1		T55	1		T22	28
valid_sources[0x02]	840	1			T22	22		T18	81		T34	12
valid_sources[0x03]	1397	1			T1	1		T32	1		T55	1
valid_sources[0x04]	679	1			T14	2		T32	1		T22	27
valid_sources[0x05]	807	1			T37	1		T32	1		T22	15
valid_sources[0x06]	805	1			T4	2		T64	1		T22	30
valid_sources[0x07]	645	1			T14	6		T22	15		T18	9
valid_sources[0x08]	743	1			T10	1		T22	16		T18	56
valid_sources[0x09]	784	1			T7	2		T22	30		T33	1
valid_sources[0x0a]	762	1			T22	18		T18	61		T34	4
valid_sources[0x0b]	528	1			T32	1		T22	23		T18	1
valid_sources[0x0c]	547	1			T7	4		T64	1		T22	19
valid_sources[0x0d]	591	1			T22	23		T18	9		T34	5
valid_sources[0x0e]	679	1			T31	2		T22	14		T18	89
valid_sources[0x0f]	776	1			T11	5		T7	3		T31	5
valid_sources[0x10]	385	1			T22	7		T18	2		T34	12
valid_sources[0x11]	827	1			T64	1		T22	15		T87	1
valid_sources[0x12]	714	1			T22	31		T18	64		T34	6
valid_sources[0x13]	1076	1			T7	2		T22	34		T23	1
valid_sources[0x14]	616	1			T7	2		T22	33		T23	1
valid_sources[0x15]	1041	1			T53	1		T22	16		T33	2
valid_sources[0x16]	1017	1			T12	1		T7	6		T22	25
valid_sources[0x17]	624	1			T22	20		T133	1		T18	1
valid_sources[0x18]	886	1			T64	1		T32	1		T138	1
valid_sources[0x19]	628	1			T31	1		T47	1		T22	22
valid_sources[0x1a]	908	1			T22	25		T23	128		T87	1
valid_sources[0x1b]	569	1			T7	1		T22	32		T67	3
valid_sources[0x1c]	809	1			T56	2		T22	15		T67	2
valid_sources[0x1d]	612	1			T6	2		T7	10		T22	19
valid_sources[0x1e]	789	1			T21	1		T22	18		T18	43
valid_sources[0x1f]	712	1			T7	1		T14	4		T22	13
valid_sources[0x20]	628	1			T22	15		T18	21		T34	6
valid_sources[0x21]	687	1			T22	12		T23	1		T33	2
valid_sources[0x22]	751	1			T22	13		T18	18		T34	6
valid_sources[0x23]	1063	1			T55	1		T22	18		T18	15
valid_sources[0x24]	681	1			T7	4		T22	22		T18	21
valid_sources[0x25]	652	1			T10	1		T7	1		T14	2
valid_sources[0x26]	746	1			T22	14		T18	43		T34	8
valid_sources[0x27]	583	1			T32	1		T22	26		T18	47
valid_sources[0x28]	846	1			T55	2		T22	13		T18	27
valid_sources[0x29]	460	1			T7	6		T37	1		T22	18
valid_sources[0x2a]	566	1			T37	1		T22	26		T133	1
valid_sources[0x2b]	634	1			T22	25		T33	1		T18	12
valid_sources[0x2c]	891	1			T31	1		T22	32		T104	5
valid_sources[0x2d]	628	1			T7	3		T22	22		T18	20
valid_sources[0x2e]	626	1			T7	5		T14	4		T56	2
valid_sources[0x2f]	731	1			T22	21		T23	2		T18	27
valid_sources[0x30]	975	1			T7	8		T22	9		T18	16
valid_sources[0x31]	703	1			T22	29		T18	43		T34	1
valid_sources[0x32]	623	1			T22	19		T18	18		T34	3
valid_sources[0x33]	852	1			T64	1		T55	1		T22	18
valid_sources[0x34]	609	1			T14	2		T22	13		T18	1
valid_sources[0x35]	542	1			T22	18		T139	1		T18	42
valid_sources[0x36]	1026	1			T60	1		T22	19		T18	4
valid_sources[0x37]	614	1			T22	12		T33	2		T18	8
valid_sources[0x38]	688	1			T32	1		T22	9		T133	2
valid_sources[0x39]	431	1			T7	1		T14	4		T22	22
valid_sources[0x3a]	1092	1			T22	15		T133	1		T18	21
valid_sources[0x3b]	828	1			T22	30		T33	2		T18	167
valid_sources[0x3c]	595	1			T22	27		T18	8		T49	2
valid_sources[0x3d]	953	1			T37	1		T32	1		T60	4
valid_sources[0x3e]	502	1			T138	3		T22	18		T33	1
valid_sources[0x3f]	791	1			T14	1		T22	26		T69	1
valid_sources[0x40]	1326	1			T7	2		T22	22		T18	37
valid_sources[0x41]	646	1			T7	3		T22	24		T18	4
valid_sources[0x42]	582	1			T32	1		T52	1		T22	20
valid_sources[0x43]	710	1			T7	4		T22	15		T18	25
valid_sources[0x44]	876	1			T7	3		T31	1		T14	2
valid_sources[0x45]	762	1			T7	1		T8	4		T14	6
valid_sources[0x46]	935	1			T14	5		T22	18		T18	22
valid_sources[0x47]	878	1			T14	1		T22	14		T33	1
valid_sources[0x48]	668	1			T22	28		T18	83		T34	12
valid_sources[0x49]	1001	1			T7	1		T32	1		T22	23
valid_sources[0x4a]	667	1			T7	7		T55	2		T22	24
valid_sources[0x4b]	644	1			T22	25		T18	9		T34	5
valid_sources[0x4c]	578	1			T22	32		T23	1		T33	1
valid_sources[0x4d]	611	1			T7	7		T8	1		T31	2
valid_sources[0x4e]	642	1			T14	2		T22	17		T33	1
valid_sources[0x4f]	950	1			T22	13		T33	1		T18	11
valid_sources[0x50]	631	1			T7	4		T22	23		T18	6
valid_sources[0x51]	855	1			T7	1		T32	1		T22	33
valid_sources[0x52]	893	1			T7	1		T14	12		T22	19
valid_sources[0x53]	699	1			T31	1		T22	17		T18	32
valid_sources[0x54]	823	1			T14	4		T55	1		T22	16
valid_sources[0x55]	724	1			T60	5		T22	22		T18	50
valid_sources[0x56]	565	1			T7	6		T55	1		T22	12
valid_sources[0x57]	975	1			T12	1		T14	5		T64	1
valid_sources[0x58]	654	1			T7	1		T22	33		T18	42
valid_sources[0x59]	563	1			T22	19		T23	3		T18	32
valid_sources[0x5a]	532	1			T22	19		T18	43		T34	33
valid_sources[0x5b]	452	1			T22	15		T23	4		T18	4
valid_sources[0x5c]	1105	1			T14	8		T32	2		T22	28
valid_sources[0x5d]	731	1			T22	39		T34	11		T116	1
valid_sources[0x5e]	433	1			T14	1		T138	1		T22	28
valid_sources[0x5f]	637	1			T30	1		T22	28		T18	64
valid_sources[0x60]	800	1			T22	18		T18	8		T34	19
valid_sources[0x61]	751	1			T22	32		T18	55		T34	4
valid_sources[0x62]	747	1			T22	19		T87	2		T18	2
valid_sources[0x63]	770	1			T22	20		T18	1		T34	9
valid_sources[0x64]	771	1			T31	1		T22	20		T33	1
valid_sources[0x65]	680	1			T22	27		T23	5		T104	1
valid_sources[0x66]	781	1			T7	4		T14	5		T22	19
valid_sources[0x67]	695	1			T22	21		T18	26		T34	1
valid_sources[0x68]	844	1			T22	21		T18	22		T34	3
valid_sources[0x69]	451	1			T14	5		T64	2		T53	1
valid_sources[0x6a]	405	1			T7	8		T14	5		T21	1
valid_sources[0x6b]	534	1			T21	1		T22	17		T139	2
valid_sources[0x6c]	913	1			T22	13		T23	2		T133	1
valid_sources[0x6d]	785	1			T7	1		T22	14		T18	10
valid_sources[0x6e]	498	1			T27	3		T8	3		T22	12
valid_sources[0x6f]	658	1			T64	1		T22	36		T18	23
valid_sources[0x70]	789	1			T37	1		T22	15		T23	3
valid_sources[0x71]	633	1			T1	4		T7	6		T22	17
valid_sources[0x72]	674	1			T14	9		T22	12		T33	1
valid_sources[0x73]	518	1			T7	5		T64	1		T55	2
valid_sources[0x74]	632	1			T64	1		T22	13		T23	57
valid_sources[0x75]	839	1			T7	5		T8	3		T22	29
valid_sources[0x76]	822	1			T22	24		T34	6		T9	57
valid_sources[0x77]	750	1			T55	3		T22	24		T18	3
valid_sources[0x78]	777	1			T14	4		T21	2		T22	28
valid_sources[0x79]	633	1			T7	2		T8	5		T14	3
valid_sources[0x7a]	666	1			T22	22		T18	4		T34	5
valid_sources[0x7b]	514	1			T7	1		T14	1		T22	14
valid_sources[0x7c]	522	1			T22	38		T18	70		T34	8
valid_sources[0x7d]	616	1			T7	10		T14	4		T22	30
valid_sources[0x7e]	454	1			T22	34		T18	4		T34	1
valid_sources[0x7f]	412	1			T22	23		T18	8		T34	11
valid_sources[0x80]	524	1			T28	3		T22	18		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40653

1

T7

41

T8

8

T14

13

values[0x0]

all_enables

biggest_size

55008

1

T1

8

T13

1

T27

3

values[0x1]

all_enables

biggest_size

52419

1

T1

1

T2

1

T3

1