Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13588637

1

T2

18632

T3

2419

T4

396

full_word

56699994

1

T2

186608

T3

23813

T4

4073

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70288321	1			T2	205240		T3	26232		T4	4469
auto[TlIntgErrCmd]	107	1			T57	6		T58	4		T59	4
auto[TlIntgErrData]	102	1			T57	8		T58	3		T59	4
auto[TlIntgErrBoth]	101	1			T57	6		T58	3		T59	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32153555

1

T2

102525

T3

13121

T4

2240

auto[1]

38135076

1

T2

102715

T3

13111

T4

2229

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6468819	1			T2	9224		T3	1260		T4	200
auto[TlIntgErrNone]	partial	auto[1]	7119531	1			T2	9408		T3	1159		T4	196
auto[TlIntgErrNone]	full_word	auto[0]	25684593	1			T2	93301		T3	11861		T4	2040
auto[TlIntgErrNone]	full_word	auto[1]	31015378	1			T2	93307		T3	11952		T4	2033
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T57	2		T58	2		T59	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T57	4		T58	2		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T128	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T123	1		T126	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T57	4		T58	2		T59	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T57	3		T58	1		T59	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T57	1		T128	1		T130	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T121	2		T126	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T57	4		T59	1		T123	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T57	1		T58	3		T123	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T59	1		T123	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T57	1		T132	1		T129	1