Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	699637	1			T27	257		T28	7825		T29	336
auto[1]	10098141	1			T2	86179		T3	227		T6	376
auto[2]	598348	1			T27	154		T28	7277		T29	268
auto[3]	10002522	1			T2	86465		T3	250		T6	365

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14425015	1			T2	142810		T3	334		T6	487
auto[1]	1999313	1			T2	14147		T3	64		T6	112
auto[2]	1998004	1			T2	14201		T3	64		T6	116
auto[3]	2976316	1			T2	1486		T3	15		T6	26

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9237483

1

T2

47

T3

477

T6

741

auto[1]

12161165

1

T2

172597

T10

1

T27

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	301301	1			T28	6442		T29	13		T34	1
auto[0]	auto[0]	auto[1]	31174	1			T27	2		T28	644		T29	46
auto[0]	auto[0]	auto[2]	30744	1			T27	2		T28	666		T29	45
auto[0]	auto[0]	auto[3]	7509	1			T27	250		T28	65		T29	232
auto[0]	auto[1]	auto[0]	3517262	1			T2	22		T3	168		T6	254
auto[0]	auto[1]	auto[1]	366526	1			T2	1		T3	48		T6	51
auto[0]	auto[1]	auto[2]	348938	1			T2	2		T3	8		T6	55
auto[0]	auto[1]	auto[3]	65292	1			T3	3		T6	16		T12	54
auto[0]	auto[2]	auto[0]	262390	1			T28	6081		T29	16		T35	3825
auto[0]	auto[2]	auto[1]	27106	1			T27	20		T28	574		T29	50
auto[0]	auto[2]	auto[2]	25736	1			T27	4		T28	565		T29	36
auto[0]	auto[2]	auto[3]	5911	1			T27	130		T28	49		T29	166
auto[0]	auto[3]	auto[0]	3472426	1			T2	20		T3	166		T6	233
auto[0]	auto[3]	auto[1]	345778	1			T2	1		T3	16		T6	61
auto[0]	auto[3]	auto[2]	363418	1			T2	1		T3	56		T6	61
auto[0]	auto[3]	auto[3]	65972	1			T3	12		T6	10		T12	80
auto[1]	auto[0]	auto[0]	11091	1			T28	7		T103	586		T35	2
auto[1]	auto[0]	auto[1]	49007	1			T103	2844		T134	2649		T135	2437
auto[1]	auto[0]	auto[2]	48631	1			T28	1		T103	2921		T136	1
auto[1]	auto[0]	auto[3]	220180	1			T27	3		T103	12361		T134	12072
auto[1]	auto[1]	auto[0]	3425408	1			T2	71372		T7	14		T31	55
auto[1]	auto[1]	auto[1]	585433	1			T2	6990		T7	2		T31	2
auto[1]	auto[1]	auto[2]	560292	1			T2	7073		T24	1		T31	3
auto[1]	auto[1]	auto[3]	1228990	1			T2	719		T24	1		T51	9254
auto[1]	auto[2]	auto[0]	9326	1			T28	7		T103	305		T35	2
auto[1]	auto[2]	auto[1]	40881	1			T103	1683		T134	2446		T135	2319
auto[1]	auto[2]	auto[2]	41095	1			T28	1		T103	2978		T134	2213
auto[1]	auto[2]	auto[3]	185903	1			T103	13577		T134	10295		T135	9515
auto[1]	auto[3]	auto[0]	3425811	1			T2	71396		T10	1		T7	13
auto[1]	auto[3]	auto[1]	553408	1			T2	7155		T31	5		T14	2
auto[1]	auto[3]	auto[2]	579150	1			T2	7125		T7	1		T31	2
auto[1]	auto[3]	auto[3]	1196559	1			T2	767		T24	1		T51	9130