Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	335146087	223515	0	0
ctrl_regwen_rd_A	335146087	3786	0	0
exec_rd_A	335146087	3593	0	0
exec_regwen_rd_A	335146087	3899	0	0
readback_rd_A	335146087	3063	0	0
readback_regwen_rd_A	335146087	2615	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335146087	223515	0	0
T18	0	10452	0	0
T22	121331	7826	0	0
T23	34156	1681	0	0
T29	24344	0	0	0
T33	495431	0	0	0
T34	0	2533	0	0
T38	0	1565	0	0
T44	65614	0	0	0
T45	0	4426	0	0
T46	0	8243	0	0
T48	0	2195	0	0
T49	0	1516	0	0
T50	0	9653	0	0
T65	171886	0	0	0
T66	22383	0	0	0
T67	229939	0	0	0
T68	203663	0	0	0
T69	59336	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335146087	3786	0	0
T9	51232	0	0	0
T34	53538	184	0	0
T35	384457	0	0	0
T38	0	98	0	0
T41	0	82	0	0
T42	0	530	0	0
T105	0	348	0	0
T106	0	57	0	0
T107	0	155	0	0
T108	0	128	0	0
T109	0	379	0	0
T110	0	210	0	0
T111	4524	0	0	0
T112	228831	0	0	0
T113	14371	0	0	0
T114	375330	0	0	0
T115	174029	0	0	0
T116	470158	0	0	0
T117	359089	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335146087	3593	0	0
T9	51232	0	0	0
T34	53538	229	0	0
T35	384457	0	0	0
T38	0	131	0	0
T41	0	53	0	0
T42	0	528	0	0
T105	0	274	0	0
T106	0	80	0	0
T107	0	114	0	0
T108	0	94	0	0
T109	0	355	0	0
T110	0	212	0	0
T111	4524	0	0	0
T112	228831	0	0	0
T113	14371	0	0	0
T114	375330	0	0	0
T115	174029	0	0	0
T116	470158	0	0	0
T117	359089	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335146087	3899	0	0
T9	51232	0	0	0
T34	53538	204	0	0
T35	384457	0	0	0
T38	0	123	0	0
T41	0	72	0	0
T42	0	591	0	0
T105	0	306	0	0
T106	0	77	0	0
T107	0	147	0	0
T108	0	178	0	0
T109	0	380	0	0
T110	0	202	0	0
T111	4524	0	0	0
T112	228831	0	0	0
T113	14371	0	0	0
T114	375330	0	0	0
T115	174029	0	0	0
T116	470158	0	0	0
T117	359089	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335146087	3063	0	0
T9	51232	0	0	0
T34	53538	216	0	0
T35	384457	0	0	0
T38	0	145	0	0
T41	0	72	0	0
T42	0	521	0	0
T105	0	367	0	0
T106	0	94	0	0
T107	0	99	0	0
T108	0	144	0	0
T109	0	304	0	0
T110	0	145	0	0
T111	4524	0	0	0
T112	228831	0	0	0
T113	14371	0	0	0
T114	375330	0	0	0
T115	174029	0	0	0
T116	470158	0	0	0
T117	359089	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335146087	2615	0	0
T9	51232	0	0	0
T34	53538	127	0	0
T35	384457	0	0	0
T38	0	142	0	0
T41	0	35	0	0
T42	0	499	0	0
T105	0	266	0	0
T106	0	64	0	0
T107	0	87	0	0
T108	0	133	0	0
T109	0	326	0	0
T110	0	188	0	0
T111	4524	0	0	0
T112	228831	0	0	0
T113	14371	0	0	0
T114	375330	0	0	0
T115	174029	0	0	0
T116	470158	0	0	0
T117	359089	0	0	0