Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.77	97.30	84.03			93.75	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram	94.47	97.30	86.84			93.75	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	97.30	86.84			93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	98.89	92.31	97.66	100.00	93.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
u_err	100.00	100.00	100.00			100.00	100.00
u_reqfifo	96.82	100.00	94.12	90.00		100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	97.05	100.00	95.24	90.00		100.00	100.00
u_sram_byte	97.23	98.83	94.94		100.00	92.38	100.00
u_sramreqfifo	92.97	100.00	84.85	90.00		90.00	100.00

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		74	72	97.30
CONT_ASSIGN	93	1	1	100.00
ALWAYS	96	4	3	75.00
CONT_ASSIGN	111	1	1	100.00
ALWAYS	126	4	3	75.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	269	8	8	100.00
ALWAYS	289	6	6	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
ALWAYS	352	3	3	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
ALWAYS	412	6	6	100.00
ALWAYS	424	5	5	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
ALWAYS	479	3	3	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	510	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
96	1	1
97	1	1
98	1	1
99	0	1
			MISSING_ELSE
111	1	1
126	1	1
127	1	1
128	1	1
129	0	1
			MISSING_ELSE
135	1	1
141	1	1
148	1	1
173	1	1
185	1	1
262	1	1
263	1	1
264	1	1
269	1	1
271	1	1
272	1	1
274	1	1
275	1	1
276	1	1
279	1	1
282	1	1
289	1	1
291	1	1
292	1	1
293	1	1
295	1	1
298	1	1
303	1	1
307	1	1
326	1	1
331	1	1
337	1	1
349	1	1
352	1	1
353	1	1
355	1	1
359	1	1
379	1	1
380	1	1
381	1	1
382	1	1
412	1	1
413	1	1
415	1	1
416	1	1
417	1	1
418	1	1
			MISSING_ELSE
424	1	1
425	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
445	1	1
446	1	1
448	1	1
449	1	1
456	1	1
459	1	1
463	1	1
464	1	1
466	1	1
473	1	1
479	1	1
483	1	1
485	1	1
			MISSING_ELSE
500	1	1
505	1	1
510		unreachable

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	119	100	84.03
Logical	119	100	84.03
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       128
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       135
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

 LINE       141
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       141
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       173
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T4,T5,T7
0	0	0	1	0	0	Covered	T7,T14,T17
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       262
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T31,T32
1	1	Covered	T2,T3,T4

 LINE       263
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       264
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T2,T3,T4

 LINE       275
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       292
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       293
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T7,T14,T17
1	0	Not Covered

 LINE       303
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T7,T14,T17
1	1	1	0	Covered	T27,T28,T29
1	1	1	1	Covered	T2,T3,T4

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       331
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       331
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T3,T4

 LINE       337
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T35,T36

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T34,T35,T36

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T31,T32
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T14,T17
1	1	1	Covered	T22,T23,T18

 LINE       359
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       359
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       359
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       359
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T7,T14,T17

 LINE       359
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T5,T27,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       359
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T22,T23,T18
1	0	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T27,T28,T29
1	1	0	Covered	T7,T14,T17
1	1	1	Covered	T2,T3,T4

 LINE       381
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       382
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       418
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       418
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       449
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       466
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       505
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       505
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T14,T17
1	1	Covered	T2,T3,T4

 LINE       505
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		32	30	93.75
TERNARY	141	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	337	3	3	100.00
TERNARY	382	2	2	100.00
TERNARY	505	2	2	100.00
IF	126	3	2	66.67
IF	271	4	4	100.00
IF	291	3	3	100.00
IF	352	2	2	100.00
IF	415	2	2	100.00
IF	427	2	2	100.00
IF	96	3	2	66.67
IF	483	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	141	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	331	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	337	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	382	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	505	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if ((!rst_ni))
-2-:	128	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	if (reqfifo_rvalid)
-2-:	272	if (reqfifo_rdata.error)
-3-:	275	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T7,T14,T17
1	0	1	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	if (reqfifo_rvalid)
-2-:	292	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	352	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	415	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (readback_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	483	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	333874513	333779194	0	0
DataIntgOptions_A	892	892	0	0
ReqOutKnown_A	333874513	333779194	0	0
SramDwHasByteGranularity_A	892	892	0	0
SramDwIsMultipleOfTlulWidth_A	892	892	0	0
TlOutKnownIfFifoKnown_A	333874513	333779194	0	0
TlOutValidKnown_A	333874513	333779194	0	0
WdataOutKnown_A	333874513	333779194	0	0
WeOutKnown_A	333874513	333779194	0	0
WmaskOutKnown_A	333874513	333779194	0	0
adapterNoReadOrWrite	892	892	0	0
rvalidHighReqFifoEmpty	333874513	35878511	0	0
rvalidHighWhenRspFifoFull	333874513	35878511	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	35878511	0	0
T2	248985	111933	0	0
T3	183186	14280	0	0
T4	36102	2436	0	0
T5	29094	2492	0	0
T6	4627	447	0	0
T10	6583	1628	0	0
T11	22989	2675	0	0
T12	8378	960	0	0
T13	3572	0	0	0
T24	0	5684	0	0
T27	16409	1864	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	35878511	0	0
T2	248985	111933	0	0
T3	183186	14280	0	0
T4	36102	2436	0	0
T5	29094	2492	0	0
T6	4627	447	0	0
T10	6583	1628	0	0
T11	22989	2675	0	0
T12	8378	960	0	0
T13	3572	0	0	0
T24	0	5684	0	0
T27	16409	1864	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		74	72	97.30
CONT_ASSIGN	93	1	1	100.00
ALWAYS	96	4	3	75.00
CONT_ASSIGN	111	1	1	100.00
ALWAYS	126	4	3	75.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	269	8	8	100.00
ALWAYS	289	6	6	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
ALWAYS	352	3	3	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
ALWAYS	412	6	6	100.00
ALWAYS	424	5	5	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
ALWAYS	479	3	3	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	510	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
96	1	1
97	1	1
98	1	1
99	0	1
			MISSING_ELSE
111	1	1
126	1	1
127	1	1
128	1	1
129	0	1
			MISSING_ELSE
135	1	1
141	1	1
148	1	1
173	1	1
185	1	1
262	1	1
263	1	1
264	1	1
269	1	1
271	1	1
272	1	1
274	1	1
275	1	1
276	1	1
279	1	1
282	1	1
289	1	1
291	1	1
292	1	1
293	1	1
295	1	1
298	1	1
303	1	1
307	1	1
326	1	1
331	1	1
337	1	1
349	1	1
352	1	1
353	1	1
355	1	1
359	1	1
379	1	1
380	1	1
381	1	1
382	1	1
412	1	1
413	1	1
415	1	1
416	1	1
417	1	1
418	1	1
			MISSING_ELSE
424	1	1
425	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
445	1	1
446	1	1
448	1	1
449	1	1
456	1	1
459	1	1
463	1	1
464	1	1
466	1	1
473	1	1
479	1	1
483	1	1
485	1	1
			MISSING_ELSE
500	1	1
505	1	1
510		unreachable

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Total	Covered	Percent
Conditions	114	99	86.84
Logical	114	99	86.84
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       128
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       135
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

 LINE       141
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       141
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       173
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T4,T5,T7
0	0	0	1	0	0	Covered	T7,T14,T17
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Excluded		VC_COV_UNR

 LINE       262
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T31,T32
1	1	Covered	T2,T3,T4

 LINE       263
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       264
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded	T1,T2,T3	VC_COV_UNR
1	0	Covered	T31,T32,T33
1	1	Covered	T2,T3,T4

 LINE       275
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       292
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       293
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T7,T14,T17
1	0	Not Covered

 LINE       303
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Covered	T7,T14,T17
1	1	1	0	Covered	T27,T28,T29
1	1	1	1	Covered	T2,T3,T4

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       331
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       331
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T3,T4

 LINE       337
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T35,T36

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T34,T35,T36

 LINE       337
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T31,T32
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T14,T17
1	1	1	Covered	T22,T23,T18

 LINE       359
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       359
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       359
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       359
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       359
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T7,T14,T17

 LINE       359
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T5,T27,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       359
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T22,T23,T18
1	0	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T27,T28,T29
1	1	0	Covered	T7,T14,T17
1	1	1	Covered	T2,T3,T4

 LINE       381
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       382
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       418
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       418
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       449
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       466
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T2,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       505
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       505
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T14,T17
1	1	Covered	T2,T3,T4

 LINE       505
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		32	30	93.75
TERNARY	141	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	337	3	3	100.00
TERNARY	382	2	2	100.00
TERNARY	505	2	2	100.00
IF	126	3	2	66.67
IF	271	4	4	100.00
IF	291	3	3	100.00
IF	352	2	2	100.00
IF	415	2	2	100.00
IF	427	2	2	100.00
IF	96	3	2	66.67
IF	483	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	141	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	331	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	337	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	382	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	505	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if ((!rst_ni))
-2-:	128	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	if (reqfifo_rvalid)
-2-:	272	if (reqfifo_rdata.error)
-3-:	275	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T7,T14,T17
1	0	1	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	if (reqfifo_rvalid)
-2-:	292	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	352	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	415	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (readback_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	483	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	333874513	333779194	0	0
DataIntgOptions_A	892	892	0	0
ReqOutKnown_A	333874513	333779194	0	0
SramDwHasByteGranularity_A	892	892	0	0
SramDwIsMultipleOfTlulWidth_A	892	892	0	0
TlOutKnownIfFifoKnown_A	333874513	333779194	0	0
TlOutValidKnown_A	333874513	333779194	0	0
WdataOutKnown_A	333874513	333779194	0	0
WeOutKnown_A	333874513	333779194	0	0
WmaskOutKnown_A	333874513	333779194	0	0
adapterNoReadOrWrite	892	892	0	0
rvalidHighReqFifoEmpty	333874513	35878511	0	0
rvalidHighWhenRspFifoFull	333874513	35878511	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	333779194	0	0
T1	1002	948	0	0
T2	248985	248926	0	0
T3	183186	183123	0	0
T4	36102	36017	0	0
T5	29094	29031	0	0
T6	4627	4573	0	0
T10	6583	6532	0	0
T11	22989	22925	0	0
T12	8378	8307	0	0
T13	3572	3507	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	35878511	0	0
T2	248985	111933	0	0
T3	183186	14280	0	0
T4	36102	2436	0	0
T5	29094	2492	0	0
T6	4627	447	0	0
T10	6583	1628	0	0
T11	22989	2675	0	0
T12	8378	960	0	0
T13	3572	0	0	0
T24	0	5684	0	0
T27	16409	1864	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	333874513	35878511	0	0
T2	248985	111933	0	0
T3	183186	14280	0	0
T4	36102	2436	0	0
T5	29094	2492	0	0
T6	4627	447	0	0
T10	6583	1628	0	0
T11	22989	2675	0	0
T12	8378	960	0	0
T13	3572	0	0	0
T24	0	5684	0	0
T27	16409	1864	0	0