Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	144053662	1			T1	385618		T2	2038		T3	280508
instr_valid_dis	114253581	1			T1	385618		T2	2038		T3	280508
instr_en	20047569	1			T12	34112		T17	27190		T18	321630

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10930462	1			T4	32164		T10	51484		T12	68678
sram_ifetch_valid_disable	113775799	1			T1	385618		T2	2038		T3	280508
sram_ifetch_enable	19347401	1			T4	120832		T10	29942		T12	94900

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	144053662	1			T1	385618		T2	2038		T3	280508
hw_debug_en_valid_off	113218341	1			T1	385618		T2	2038		T3	280508
hw_debug_en_on	20614475	1			T4	81268		T10	18932		T12	134842

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113775799	1			T1	385618		T2	2038		T3	280508
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101373287	1			T1	385618		T2	2038		T3	280508
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8303230	1			T12	3452		T18	255118		T32	43666
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4758078	1			T4	32164		T10	32552		T12	21156
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1656776	1			T4	32164		T10	32552		T17	32714
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2439000	1			T12	21156		T18	12576		T22	13056
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3753189	1			T10	18932		T12	47522		T16	58
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1611275	1			T10	18932		T12	29820		T16	58
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1181290	1			T18	15270		T32	1352		T22	534
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8701910	1			T4	81268		T18	60322		T32	23464
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3245390	1			T4	81268		T33	37076		T53	106668
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3641210	1			T18	60322		T32	23464		T22	19294

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7104031	1			T12	9504		T17	27190		T18	38666
lc_exec_en	8159376	1			T12	87320		T17	113054		T18	37718
valid_exec_dis	110278101	1			T1	385618		T2	2038		T3	280508
invalid_exec_dis	30277863	1			T4	152996		T10	81426		T12	163578