Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43681182	1			T1	35260		T2	56		T3	127485
triple_byte_access	2543587	1			T1	31588		T2	124		T3	2517
halfword_access	3819826	1			T1	47343		T2	268		T3	3894
byte_access	5097774	1			T1	62796		T2	396		T3	5086
zero_access	1281880	1			T1	15822		T2	175		T3	1272

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28154880

1

T1

95974

T2

352

T3

70017

auto[1]

28269369

1

T1

96835

T2

667

T3

70237

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21790304	1			T1	17478		T2	4		T3	63624
auto[0]	triple_byte_access	1268645	1			T1	15626		T2	10		T3	1272
auto[0]	halfword_access	1903704	1			T1	23485		T2	55		T3	1943
auto[0]	byte_access	2547566	1			T1	31499		T2	154		T3	2543
auto[0]	zero_access	644661	1			T1	7886		T2	129		T3	635
auto[1]	word_access	21890878	1			T1	17782		T2	52		T3	63861
auto[1]	triple_byte_access	1274942	1			T1	15962		T2	114		T3	1245
auto[1]	halfword_access	1916122	1			T1	23858		T2	213		T3	1951
auto[1]	byte_access	2550208	1			T1	31297		T2	242		T3	2543
auto[1]	zero_access	637219	1			T1	7936		T2	46		T3	637