Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13728741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55718941

1

T1

3250

T2

304163

T3

6653

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34614040	1			T1	1792		T2	167390		T3	4100
values[0x0]	16042745	1			T1	883		T2	80576		T3	1899
values[0x1]	18790897	1			T1	917		T2	86528		T3	2167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6841438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62606244

1

T1

3440

T2

319460

T3

7416

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	277275	1			T1	67		T2	1188		T8	32
valid_sources[0x01]	267120	1			T2	1804		T8	98		T9	46
valid_sources[0x02]	244203	1			T1	25		T2	1034		T8	37
valid_sources[0x03]	279795	1			T1	41		T2	1509		T8	61
valid_sources[0x04]	253624	1			T1	24		T2	1130		T8	43
valid_sources[0x05]	307118	1			T2	1294		T8	51		T10	7
valid_sources[0x06]	299394	1			T2	1188		T8	47		T10	14
valid_sources[0x07]	294256	1			T2	1385		T8	78		T10	39
valid_sources[0x08]	270970	1			T2	1211		T8	30		T10	12
valid_sources[0x09]	294388	1			T2	1483		T8	96		T10	30
valid_sources[0x0a]	235305	1			T2	1224		T8	68		T10	20
valid_sources[0x0b]	236184	1			T2	1173		T8	62		T10	20
valid_sources[0x0c]	309311	1			T2	1066		T8	51		T10	28
valid_sources[0x0d]	244161	1			T2	1669		T8	71		T10	10
valid_sources[0x0e]	285893	1			T2	1110		T8	37		T10	22
valid_sources[0x0f]	259104	1			T2	1310		T8	54		T10	18
valid_sources[0x10]	324960	1			T1	289		T2	1344		T8	53
valid_sources[0x11]	275994	1			T1	13		T2	1326		T8	111
valid_sources[0x12]	273681	1			T2	1215		T8	34		T9	9
valid_sources[0x13]	306479	1			T2	1391		T8	53		T10	41
valid_sources[0x14]	292044	1			T2	1313		T8	72		T10	8
valid_sources[0x15]	287012	1			T2	1454		T8	67		T10	15
valid_sources[0x16]	239664	1			T2	951		T8	49		T10	25
valid_sources[0x17]	277208	1			T2	1180		T8	74		T10	6
valid_sources[0x18]	265213	1			T1	161		T2	1309		T8	34
valid_sources[0x19]	284742	1			T2	1316		T8	76		T10	29
valid_sources[0x1a]	263272	1			T1	5		T2	1332		T8	42
valid_sources[0x1b]	272198	1			T2	1251		T8	50		T10	7
valid_sources[0x1c]	261021	1			T1	6		T2	1287		T8	44
valid_sources[0x1d]	241653	1			T2	1333		T8	54		T10	9
valid_sources[0x1e]	255908	1			T2	1373		T8	77		T10	30
valid_sources[0x1f]	247263	1			T2	1440		T8	99		T10	36
valid_sources[0x20]	237070	1			T1	39		T2	1348		T8	49
valid_sources[0x21]	345948	1			T2	1439		T8	66		T10	65
valid_sources[0x22]	273745	1			T2	1006		T8	56		T10	4
valid_sources[0x23]	234835	1			T1	44		T2	1158		T8	62
valid_sources[0x24]	242341	1			T2	1195		T8	57		T9	146
valid_sources[0x25]	318988	1			T2	1425		T8	65		T10	12
valid_sources[0x26]	290402	1			T2	1291		T8	49		T9	38
valid_sources[0x27]	269284	1			T1	59		T2	1225		T8	85
valid_sources[0x28]	282961	1			T2	1570		T8	85		T10	31
valid_sources[0x29]	294023	1			T2	1186		T8	37		T10	5
valid_sources[0x2a]	270848	1			T1	146		T2	1215		T8	68
valid_sources[0x2b]	241523	1			T2	1463		T8	52		T10	36
valid_sources[0x2c]	279383	1			T1	47		T2	1123		T8	74
valid_sources[0x2d]	237303	1			T2	1376		T8	51		T10	41
valid_sources[0x2e]	273997	1			T2	1694		T8	68		T10	29
valid_sources[0x2f]	364908	1			T2	1158		T8	72		T10	45
valid_sources[0x30]	276066	1			T2	1486		T8	72		T10	17
valid_sources[0x31]	257911	1			T2	1452		T8	38		T10	48
valid_sources[0x32]	307788	1			T2	1241		T8	52		T10	50
valid_sources[0x33]	246381	1			T2	1313		T8	47		T10	20
valid_sources[0x34]	256002	1			T2	1464		T8	61		T10	23
valid_sources[0x35]	245014	1			T2	1550		T8	57		T10	25
valid_sources[0x36]	307466	1			T1	49		T2	1456		T8	66
valid_sources[0x37]	298341	1			T2	1446		T8	53		T10	45
valid_sources[0x38]	264634	1			T2	1306		T8	92		T10	27
valid_sources[0x39]	247354	1			T2	1368		T8	54		T10	17
valid_sources[0x3a]	273724	1			T2	1256		T8	41		T9	31
valid_sources[0x3b]	243924	1			T2	1166		T8	59		T10	41
valid_sources[0x3c]	268009	1			T2	1028		T3	4083		T8	64
valid_sources[0x3d]	292117	1			T2	1458		T8	94		T10	49
valid_sources[0x3e]	301155	1			T2	1369		T8	120		T10	42
valid_sources[0x3f]	289170	1			T2	1297		T8	55		T10	27
valid_sources[0x40]	246627	1			T1	101		T2	1248		T8	145
valid_sources[0x41]	235811	1			T1	30		T2	1243		T8	44
valid_sources[0x42]	260295	1			T1	14		T2	1226		T8	35
valid_sources[0x43]	276495	1			T2	1304		T8	52		T10	45
valid_sources[0x44]	254043	1			T2	1389		T8	56		T10	23
valid_sources[0x45]	233158	1			T2	1329		T8	91		T10	36
valid_sources[0x46]	340935	1			T2	1417		T8	31		T10	47
valid_sources[0x47]	287165	1			T2	1340		T8	85		T10	3
valid_sources[0x48]	302097	1			T2	1251		T3	4083		T8	46
valid_sources[0x49]	245510	1			T2	1538		T8	79		T10	29
valid_sources[0x4a]	239882	1			T2	1046		T8	29		T10	23
valid_sources[0x4b]	260500	1			T2	1357		T8	66		T10	26
valid_sources[0x4c]	273921	1			T2	1256		T8	81		T10	36
valid_sources[0x4d]	253603	1			T2	1505		T8	84		T10	18
valid_sources[0x4e]	288781	1			T2	1097		T8	23		T10	11
valid_sources[0x4f]	268259	1			T2	1354		T8	55		T10	11
valid_sources[0x50]	251812	1			T2	1193		T8	60		T10	45
valid_sources[0x51]	274387	1			T1	161		T2	1334		T8	100
valid_sources[0x52]	253426	1			T1	9		T2	1317		T8	45
valid_sources[0x53]	281606	1			T2	1075		T8	41		T10	27
valid_sources[0x54]	269416	1			T2	1383		T8	23		T10	32
valid_sources[0x55]	299148	1			T2	1440		T8	63		T10	22
valid_sources[0x56]	309710	1			T2	1040		T8	48		T10	27
valid_sources[0x57]	255595	1			T2	1369		T8	60		T10	19
valid_sources[0x58]	291687	1			T1	48		T2	1273		T8	61
valid_sources[0x59]	248024	1			T2	1446		T8	59		T10	43
valid_sources[0x5a]	243868	1			T2	1265		T8	53		T9	35
valid_sources[0x5b]	293988	1			T1	43		T2	1101		T8	80
valid_sources[0x5c]	293218	1			T2	1449		T8	40		T10	23
valid_sources[0x5d]	254342	1			T2	1625		T8	53		T9	113
valid_sources[0x5e]	305909	1			T2	1311		T8	74		T10	10
valid_sources[0x5f]	262608	1			T2	1146		T8	80		T10	25
valid_sources[0x60]	326745	1			T2	1183		T8	90		T10	39
valid_sources[0x61]	300423	1			T1	39		T2	1356		T8	33
valid_sources[0x62]	236085	1			T2	1226		T8	69		T10	20
valid_sources[0x63]	261483	1			T2	1285		T8	74		T10	47
valid_sources[0x64]	293945	1			T2	1103		T8	89		T10	27
valid_sources[0x65]	287572	1			T2	1436		T8	61		T10	29
valid_sources[0x66]	291429	1			T2	1571		T8	57		T9	17
valid_sources[0x67]	237840	1			T2	1116		T8	68		T10	38
valid_sources[0x68]	249947	1			T2	1549		T8	57		T10	22
valid_sources[0x69]	273283	1			T2	1196		T8	80		T10	12
valid_sources[0x6a]	281339	1			T2	1127		T8	84		T10	18
valid_sources[0x6b]	269246	1			T2	1375		T8	30		T10	30
valid_sources[0x6c]	301360	1			T2	1282		T8	62		T10	29
valid_sources[0x6d]	263128	1			T2	1211		T8	50		T10	4
valid_sources[0x6e]	318255	1			T2	1324		T8	68		T10	14
valid_sources[0x6f]	291073	1			T2	1008		T8	28		T10	22
valid_sources[0x70]	290786	1			T2	1258		T8	38		T10	18
valid_sources[0x71]	250665	1			T2	1290		T8	77		T10	12
valid_sources[0x72]	243044	1			T2	1354		T8	87		T10	33
valid_sources[0x73]	250843	1			T2	1598		T8	85		T10	37
valid_sources[0x74]	247757	1			T2	1235		T8	59		T10	30
valid_sources[0x75]	257984	1			T2	1480		T8	21		T10	15
valid_sources[0x76]	244334	1			T2	1461		T8	91		T10	23
valid_sources[0x77]	255108	1			T1	86		T2	1105		T8	52
valid_sources[0x78]	248302	1			T2	1341		T8	29		T10	26
valid_sources[0x79]	276989	1			T2	1586		T8	61		T9	168
valid_sources[0x7a]	248858	1			T1	44		T2	1490		T8	72
valid_sources[0x7b]	252065	1			T2	1032		T8	53		T10	16
valid_sources[0x7c]	245967	1			T2	1366		T8	117		T10	21
valid_sources[0x7d]	261049	1			T2	1394		T8	42		T10	39
valid_sources[0x7e]	255975	1			T2	1140		T8	73		T10	25
valid_sources[0x7f]	277220	1			T2	1372		T8	103		T10	27
valid_sources[0x80]	239094	1			T2	1080		T8	43		T10	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27754623

1

T1

1638

T2

152188

T3

3356

values[0x0]

all_enables

biggest_size

13980518

1

T1

828

T2

75999

T3

1678

values[0x1]

all_enables

biggest_size

13983800

1

T1

784

T2

75976

T3

1619

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149298

1

T1

29

T2

1

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53776	1			T1	30		T4	253		T11	23
values[0x0]	63805	1			T1	15		T2	2		T8	5
values[0x1]	68080	1			T1	23		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158195

1

T1

30

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	651	1			T4	4		T20	16		T21	2
valid_sources[0x01]	863	1			T4	4		T20	8		T21	8
valid_sources[0x02]	848	1			T4	2		T7	1		T20	17
valid_sources[0x03]	650	1			T4	3		T20	9		T43	1
valid_sources[0x04]	593	1			T4	6		T22	1		T20	7
valid_sources[0x05]	603	1			T20	7		T21	19		T57	4
valid_sources[0x06]	516	1			T4	3		T7	2		T20	9
valid_sources[0x07]	797	1			T4	2		T20	6		T21	4
valid_sources[0x08]	816	1			T4	4		T20	11		T21	12
valid_sources[0x09]	897	1			T4	3		T14	1		T20	14
valid_sources[0x0a]	598	1			T2	1		T4	2		T20	15
valid_sources[0x0b]	920	1			T4	4		T20	12		T21	10
valid_sources[0x0c]	677	1			T4	1		T7	1		T20	13
valid_sources[0x0d]	1190	1			T4	4		T22	1		T20	17
valid_sources[0x0e]	604	1			T4	4		T7	1		T20	11
valid_sources[0x0f]	879	1			T4	1		T20	20		T21	3
valid_sources[0x10]	696	1			T4	2		T22	1		T20	9
valid_sources[0x11]	754	1			T4	3		T22	1		T20	8
valid_sources[0x12]	807	1			T4	2		T20	11		T21	12
valid_sources[0x13]	761	1			T4	4		T14	1		T20	11
valid_sources[0x14]	609	1			T4	4		T20	15		T21	25
valid_sources[0x15]	632	1			T4	4		T23	1		T7	1
valid_sources[0x16]	972	1			T6	1		T20	10		T21	26
valid_sources[0x17]	555	1			T4	1		T20	10		T21	1
valid_sources[0x18]	687	1			T4	5		T20	13		T21	19
valid_sources[0x19]	899	1			T4	4		T22	1		T20	10
valid_sources[0x1a]	798	1			T4	5		T7	1		T20	14
valid_sources[0x1b]	819	1			T4	7		T20	12		T21	12
valid_sources[0x1c]	577	1			T4	4		T20	9		T21	32
valid_sources[0x1d]	639	1			T4	3		T20	8		T21	11
valid_sources[0x1e]	677	1			T4	7		T20	8		T57	1
valid_sources[0x1f]	709	1			T4	6		T7	2		T20	8
valid_sources[0x20]	739	1			T4	9		T20	14		T21	1
valid_sources[0x21]	630	1			T4	3		T20	9		T21	11
valid_sources[0x22]	675	1			T4	4		T20	15		T21	2
valid_sources[0x23]	725	1			T4	7		T20	10		T21	2
valid_sources[0x24]	725	1			T4	1		T20	12		T21	11
valid_sources[0x25]	644	1			T4	1		T70	1		T7	1
valid_sources[0x26]	661	1			T4	5		T7	1		T20	14
valid_sources[0x27]	758	1			T4	5		T20	11		T21	5
valid_sources[0x28]	686	1			T4	6		T7	1		T22	1
valid_sources[0x29]	750	1			T4	4		T20	10		T21	10
valid_sources[0x2a]	513	1			T4	2		T20	10		T21	3
valid_sources[0x2b]	605	1			T4	6		T7	1		T20	4
valid_sources[0x2c]	771	1			T4	4		T6	1		T70	1
valid_sources[0x2d]	678	1			T4	9		T20	21		T21	2
valid_sources[0x2e]	666	1			T4	3		T27	3		T7	2
valid_sources[0x2f]	932	1			T20	13		T21	1		T16	34
valid_sources[0x30]	602	1			T4	5		T94	1		T20	11
valid_sources[0x31]	723	1			T4	2		T6	1		T22	2
valid_sources[0x32]	742	1			T20	16		T21	28		T16	24
valid_sources[0x33]	713	1			T4	6		T20	13		T21	27
valid_sources[0x34]	1166	1			T4	6		T20	6		T21	20
valid_sources[0x35]	770	1			T2	1		T4	5		T7	4
valid_sources[0x36]	640	1			T4	3		T14	1		T20	11
valid_sources[0x37]	747	1			T4	2		T70	1		T7	1
valid_sources[0x38]	598	1			T4	4		T7	1		T20	10
valid_sources[0x39]	592	1			T4	8		T20	15		T21	6
valid_sources[0x3a]	634	1			T4	2		T14	1		T124	3
valid_sources[0x3b]	850	1			T4	3		T70	1		T7	1
valid_sources[0x3c]	803	1			T4	6		T6	1		T7	1
valid_sources[0x3d]	674	1			T4	3		T7	1		T20	11
valid_sources[0x3e]	914	1			T4	5		T7	2		T20	21
valid_sources[0x3f]	482	1			T4	7		T20	7		T21	32
valid_sources[0x40]	755	1			T4	10		T22	1		T20	10
valid_sources[0x41]	851	1			T4	4		T5	21		T20	20
valid_sources[0x42]	1052	1			T4	4		T6	1		T20	11
valid_sources[0x43]	681	1			T4	6		T7	1		T20	13
valid_sources[0x44]	645	1			T4	2		T7	1		T20	6
valid_sources[0x45]	527	1			T4	5		T20	11		T16	30
valid_sources[0x46]	471	1			T4	4		T20	8		T21	18
valid_sources[0x47]	687	1			T4	3		T20	17		T21	9
valid_sources[0x48]	644	1			T4	3		T70	1		T7	1
valid_sources[0x49]	539	1			T4	5		T14	1		T22	1
valid_sources[0x4a]	742	1			T4	2		T73	6		T20	14
valid_sources[0x4b]	736	1			T4	6		T20	12		T21	12
valid_sources[0x4c]	791	1			T4	5		T6	1		T20	15
valid_sources[0x4d]	796	1			T4	6		T20	10		T21	34
valid_sources[0x4e]	588	1			T4	8		T71	5		T20	13
valid_sources[0x4f]	564	1			T4	2		T22	1		T20	10
valid_sources[0x50]	1023	1			T4	4		T20	16		T21	21
valid_sources[0x51]	615	1			T4	2		T20	13		T21	2
valid_sources[0x52]	965	1			T4	5		T20	10		T21	8
valid_sources[0x53]	627	1			T4	3		T20	8		T21	16
valid_sources[0x54]	742	1			T4	5		T25	1		T20	12
valid_sources[0x55]	719	1			T4	2		T20	7		T21	1
valid_sources[0x56]	692	1			T4	3		T14	1		T20	11
valid_sources[0x57]	953	1			T4	5		T70	1		T20	8
valid_sources[0x58]	725	1			T4	2		T20	13		T21	14
valid_sources[0x59]	738	1			T4	4		T22	1		T20	10
valid_sources[0x5a]	685	1			T4	5		T20	14		T21	18
valid_sources[0x5b]	1049	1			T4	2		T125	2		T20	19
valid_sources[0x5c]	835	1			T4	2		T22	1		T20	10
valid_sources[0x5d]	732	1			T4	2		T20	14		T21	9
valid_sources[0x5e]	925	1			T4	2		T6	1		T7	2
valid_sources[0x5f]	658	1			T4	1		T70	1		T22	2
valid_sources[0x60]	745	1			T4	9		T15	2		T20	7
valid_sources[0x61]	548	1			T4	3		T20	13		T21	9
valid_sources[0x62]	608	1			T4	3		T20	13		T21	3
valid_sources[0x63]	562	1			T4	3		T20	10		T21	19
valid_sources[0x64]	673	1			T8	8		T4	2		T72	1
valid_sources[0x65]	742	1			T4	3		T20	14		T21	4
valid_sources[0x66]	714	1			T4	2		T22	1		T20	9
valid_sources[0x67]	680	1			T4	5		T20	8		T21	11
valid_sources[0x68]	718	1			T70	1		T72	1		T20	11
valid_sources[0x69]	868	1			T4	4		T20	14		T21	10
valid_sources[0x6a]	679	1			T4	4		T22	1		T20	12
valid_sources[0x6b]	663	1			T4	4		T11	116		T20	9
valid_sources[0x6c]	766	1			T4	6		T20	13		T16	28
valid_sources[0x6d]	567	1			T4	3		T22	1		T20	12
valid_sources[0x6e]	493	1			T4	3		T20	5		T21	8
valid_sources[0x6f]	642	1			T4	5		T20	14		T21	25
valid_sources[0x70]	816	1			T4	5		T6	1		T20	6
valid_sources[0x71]	578	1			T4	4		T20	12		T21	6
valid_sources[0x72]	695	1			T4	3		T7	1		T22	2
valid_sources[0x73]	758	1			T4	5		T20	12		T21	6
valid_sources[0x74]	801	1			T4	4		T20	7		T21	7
valid_sources[0x75]	923	1			T3	2		T4	4		T23	1
valid_sources[0x76]	724	1			T4	7		T20	11		T21	5
valid_sources[0x77]	689	1			T4	3		T20	10		T21	4
valid_sources[0x78]	596	1			T4	3		T20	14		T21	4
valid_sources[0x79]	524	1			T4	1		T20	12		T21	6
valid_sources[0x7a]	637	1			T4	4		T20	15		T21	11
valid_sources[0x7b]	869	1			T4	4		T7	2		T20	22
valid_sources[0x7c]	735	1			T4	6		T20	8		T21	8
valid_sources[0x7d]	842	1			T4	3		T22	2		T20	11
valid_sources[0x7e]	772	1			T4	2		T20	13		T21	18
valid_sources[0x7f]	606	1			T4	4		T20	7		T21	4
valid_sources[0x80]	805	1			T4	5		T7	2		T20	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40807

1

T1

20

T4

226

T11

13

values[0x0]

all_enables

biggest_size

55378

1

T1

6

T2

1

T8

3

values[0x1]

all_enables

biggest_size

53113

1

T1

3

T4

340

T11

12