Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13475295

1

T1

134

T2

30331

T3

1513

full_word

51115431

1

T1

1158

T2

304163

T3

6653

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64590396	1			T1	1292		T2	334494		T3	8166
auto[TlIntgErrCmd]	114	1			T52	7		T54	5		T105	7
auto[TlIntgErrData]	117	1			T52	9		T53	5		T105	7
auto[TlIntgErrBoth]	99	1			T52	4		T53	5		T54	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29681608

1

T1

600

T2

167390

T3

4100

auto[1]

34909118

1

T1

692

T2

167104

T3

4066

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6449281	1			T1	60		T2	15202		T3	744
auto[TlIntgErrNone]	partial	auto[1]	7025714	1			T1	74		T2	15129		T3	769
auto[TlIntgErrNone]	full_word	auto[0]	23232177	1			T1	540		T2	152188		T3	3356
auto[TlIntgErrNone]	full_word	auto[1]	27883224	1			T1	618		T2	151975		T3	3297
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T52	3		T54	1		T105	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T52	3		T54	3		T105	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T112	1		T110	2		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T52	1		T54	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T52	6		T53	1		T105	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T52	2		T53	4		T105	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T111	2		T112	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T52	1		T108	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T52	1		T53	1		T54	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T52	3		T53	3		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T53	1		T115	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T107	2		T111	1		T115	1