Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	658407	1			T5	7327		T27	19642		T21	388
auto[1]	10104410	1			T1	537		T2	139646		T3	4099
auto[2]	561809	1			T5	4631		T27	17073		T21	275
auto[3]	10013397	1			T1	639		T2	139189		T3	4065

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14016229	1			T1	947		T2	232845		T3	5436
auto[1]	2033868	1			T1	111		T2	21896		T3	1216
auto[2]	2029309	1			T1	104		T2	22015		T3	1245
auto[3]	3258617	1			T1	14		T2	2079		T3	267

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8245169

1

T1

1175

T3

8157

T9

855

auto[1]

13092854

1

T1

1

T2

278835

T3

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	244807	1			T5	6057		T21	314		T31	2564
auto[0]	auto[0]	auto[1]	25021	1			T5	565		T27	1		T21	44
auto[0]	auto[0]	auto[2]	24971	1			T5	628		T21	28		T31	257
auto[0]	auto[0]	auto[3]	4487	1			T5	67		T27	3		T21	1
auto[0]	auto[1]	auto[0]	3154459	1			T1	425		T3	2774		T10	2287
auto[0]	auto[1]	auto[1]	329039	1			T1	56		T3	580		T9	2
auto[0]	auto[1]	auto[2]	318292	1			T1	48		T3	607		T9	21
auto[0]	auto[1]	auto[3]	57277	1			T1	8		T3	134		T9	285
auto[0]	auto[2]	auto[0]	216779	1			T5	3597		T21	219		T19	1
auto[0]	auto[2]	auto[1]	22051	1			T5	357		T27	1		T21	23
auto[0]	auto[2]	auto[2]	19536	1			T5	608		T21	27		T120	1
auto[0]	auto[2]	auto[3]	3569	1			T5	67		T27	3		T21	5
auto[0]	auto[3]	auto[0]	3126777	1			T1	521		T3	2657		T9	6
auto[0]	auto[3]	auto[1]	315845	1			T1	55		T3	636		T9	54
auto[0]	auto[3]	auto[2]	323844	1			T1	56		T3	636		T9	48
auto[0]	auto[3]	auto[3]	58415	1			T1	6		T3	133		T9	439
auto[1]	auto[0]	auto[0]	11997	1			T5	10		T27	648		T21	1
auto[1]	auto[0]	auto[1]	53307	1			T27	3003		T46	1458		T119	1434
auto[1]	auto[0]	auto[2]	53168	1			T27	2941		T46	1501		T32	1
auto[1]	auto[0]	auto[3]	240649	1			T27	13046		T46	6646		T119	6599
auto[1]	auto[1]	auto[0]	3626141	1			T2	116655		T3	2		T10	4
auto[1]	auto[1]	auto[1]	639659	1			T2	10293		T5	1		T27	2987
auto[1]	auto[1]	auto[2]	614397	1			T2	11657		T3	2		T11	1
auto[1]	auto[1]	auto[3]	1365146	1			T2	1041		T27	13520		T59	790
auto[1]	auto[2]	auto[0]	10105	1			T5	2		T27	617		T21	1
auto[1]	auto[2]	auto[1]	44823	1			T27	2691		T46	847		T32	1
auto[1]	auto[2]	auto[2]	44629	1			T27	2492		T46	1457		T119	1581
auto[1]	auto[2]	auto[3]	200317	1			T27	11269		T46	6287		T119	7119
auto[1]	auto[3]	auto[0]	3625164	1			T1	1		T2	116190		T3	3
auto[1]	auto[3]	auto[1]	604123	1			T2	11603		T11	2		T27	213
auto[1]	auto[3]	auto[2]	630472	1			T2	10358		T10	1		T5	1
auto[1]	auto[3]	auto[3]	1328757	1			T2	1038		T27	11566		T59	824