Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	304259897	214205	0	0
ctrl_regwen_rd_A	304259897	6127	0	0
exec_rd_A	304259897	5862	0	0
exec_regwen_rd_A	304259897	6242	0	0
readback_rd_A	304259897	4301	0	0
readback_regwen_rd_A	304259897	3649	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304259897	214205	0	0
T4	13004	906	0	0
T5	137544	0	0	0
T6	15746	0	0	0
T11	270762	0	0	0
T12	21201	0	0	0
T13	907	0	0	0
T16	0	10431	0	0
T20	0	4604	0	0
T21	0	4301	0	0
T23	64283	0	0	0
T24	2146	0	0	0
T27	120002	0	0	0
T38	0	9585	0	0
T39	0	3926	0	0
T40	0	6188	0	0
T49	0	4416	0	0
T50	0	5642	0	0
T58	0	1749	0	0
T59	275482	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304259897	6127	0	0
T18	770	0	0	0
T19	915829	0	0	0
T21	169240	330	0	0
T26	2566	0	0	0
T34	0	538	0	0
T40	0	486	0	0
T44	109423	0	0	0
T45	8741	0	0	0
T46	114150	0	0	0
T47	210067	0	0	0
T48	303502	0	0	0
T50	0	354	0	0
T57	462431	0	0	0
T96	0	177	0	0
T97	0	303	0	0
T98	0	291	0	0
T99	0	41	0	0
T100	0	86	0	0
T101	0	227	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304259897	5862	0	0
T18	770	0	0	0
T19	915829	0	0	0
T21	169240	274	0	0
T26	2566	0	0	0
T34	0	491	0	0
T40	0	408	0	0
T44	109423	0	0	0
T45	8741	0	0	0
T46	114150	0	0	0
T47	210067	0	0	0
T48	303502	0	0	0
T50	0	456	0	0
T57	462431	0	0	0
T96	0	183	0	0
T97	0	279	0	0
T98	0	218	0	0
T99	0	72	0	0
T100	0	170	0	0
T101	0	223	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304259897	6242	0	0
T18	770	0	0	0
T19	915829	0	0	0
T21	169240	266	0	0
T26	2566	0	0	0
T34	0	499	0	0
T40	0	586	0	0
T44	109423	0	0	0
T45	8741	0	0	0
T46	114150	0	0	0
T47	210067	0	0	0
T48	303502	0	0	0
T50	0	469	0	0
T57	462431	0	0	0
T96	0	223	0	0
T97	0	467	0	0
T98	0	212	0	0
T99	0	86	0	0
T100	0	151	0	0
T101	0	179	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304259897	4301	0	0
T18	770	0	0	0
T19	915829	0	0	0
T21	169240	301	0	0
T26	2566	0	0	0
T34	0	419	0	0
T40	0	439	0	0
T44	109423	0	0	0
T45	8741	0	0	0
T46	114150	0	0	0
T47	210067	0	0	0
T48	303502	0	0	0
T50	0	375	0	0
T57	462431	0	0	0
T96	0	179	0	0
T97	0	392	0	0
T98	0	233	0	0
T99	0	82	0	0
T100	0	131	0	0
T101	0	128	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304259897	3649	0	0
T18	770	0	0	0
T19	915829	0	0	0
T21	169240	232	0	0
T26	2566	0	0	0
T34	0	361	0	0
T40	0	420	0	0
T44	109423	0	0	0
T45	8741	0	0	0
T46	114150	0	0	0
T47	210067	0	0	0
T48	303502	0	0	0
T50	0	288	0	0
T57	462431	0	0	0
T96	0	165	0	0
T97	0	268	0	0
T98	0	154	0	0
T99	0	34	0	0
T100	0	90	0	0
T101	0	155	0	0