Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150453590	1			T1	536358		T2	1876		T3	53132
instr_valid_dis	116677706	1			T1	536358		T2	1876		T3	40682
instr_en	22399354	1			T3	12450		T9	400860		T14	170310

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11327631	1			T3	12450		T9	81374		T14	55626
sram_ifetch_valid_disable	117158613	1			T1	536358		T2	1876		T3	40682
sram_ifetch_enable	21967346	1			T4	146		T9	189284		T14	90322

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150453590	1			T1	536358		T2	1876		T3	53132
hw_debug_en_valid_off	119479158	1			T1	536358		T2	1876		T3	53132
hw_debug_en_on	20323364	1			T9	71638		T14	81922		T27	152830

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117158613	1			T1	536358		T2	1876		T3	40682
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103729250	1			T1	536358		T2	1876		T3	40682
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9107233	1			T9	150202		T14	24362		T27	23474
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4924182	1			T3	12450		T14	2170		T53	66088
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2165020	1			T53	27496		T127	78298		T126	72192
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1516332	1			T3	12450		T14	2170		T57	26356
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3898675	1			T9	20514		T14	14692		T27	50222
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1699554	1			T22	87408		T56	3932		T127	46572
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1266205	1			T9	20514		T14	14692		T31	6664
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7971143	1			T9	17372		T14	17388		T27	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3216608	1			T53	36760		T31	56378		T22	6788
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3061621	1			T9	17372		T14	17388		T27	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9291078	1			T9	169284		T14	90322		T27	112054
lc_exec_en	8453546	1			T9	33752		T14	49842		T27	82608
valid_exec_dis	113318386	1			T1	536358		T2	1876		T3	40682
invalid_exec_dis	33294977	1			T3	12450		T4	146		T9	270658