Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 10 0 10 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
subword_granularity_cp 5 0 5 100.00 100 1 1 0
subword_we_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
subword_access 10 0 10 100.00 100 1 1 0


Summary for Variable subword_granularity_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for subword_granularity_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ill_access 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 46191076 1 T1 243873 T2 62 T3 7695
triple_byte_access 2495475 1 T1 4814 T2 122 T3 154
halfword_access 3741633 1 T1 7150 T2 206 T3 231
byte_access 5000306 1 T1 9860 T2 371 T3 270
zero_access 1257138 1 T1 2482 T2 177 T3 68



Summary for Variable subword_we_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for subword_we_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29287843 1 T1 133833 T2 342 T3 4172
auto[1] 29397785 1 T1 134346 T2 596 T3 4246



Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for subword_access

Bins
subword_we_cpsubword_granularity_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 23048335 1 T1 121845 T2 6 T3 3837
auto[0] triple_byte_access 1243779 1 T1 2330 T2 16 T3 67
auto[0] halfword_access 1867191 1 T1 3426 T2 44 T3 113
auto[0] byte_access 2496690 1 T1 4996 T2 158 T3 118
auto[0] zero_access 631848 1 T1 1236 T2 118 T3 37
auto[1] word_access 23142741 1 T1 122028 T2 56 T3 3858
auto[1] triple_byte_access 1251696 1 T1 2484 T2 106 T3 87
auto[1] halfword_access 1874442 1 T1 3724 T2 162 T3 118
auto[1] byte_access 2503616 1 T1 4864 T2 213 T3 152
auto[1] zero_access 625290 1 T1 1246 T2 59 T3 31

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%