| T791 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2676888934 |
|
|
Jun 10 06:18:50 PM PDT 24 |
Jun 10 06:18:57 PM PDT 24 |
826528974 ps |
| T792 |
/workspace/coverage/default/14.sram_ctrl_partial_access.876248041 |
|
|
Jun 10 06:12:30 PM PDT 24 |
Jun 10 06:12:32 PM PDT 24 |
35077477 ps |
| T793 |
/workspace/coverage/default/8.sram_ctrl_alert_test.3004572754 |
|
|
Jun 10 06:10:34 PM PDT 24 |
Jun 10 06:10:35 PM PDT 24 |
11781419 ps |
| T794 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.4008317164 |
|
|
Jun 10 06:17:29 PM PDT 24 |
Jun 10 06:17:34 PM PDT 24 |
1595535026 ps |
| T795 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1196745901 |
|
|
Jun 10 06:09:23 PM PDT 24 |
Jun 10 06:09:40 PM PDT 24 |
151900303 ps |
| T796 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1172441171 |
|
|
Jun 10 06:13:47 PM PDT 24 |
Jun 10 06:13:53 PM PDT 24 |
196099025 ps |
| T797 |
/workspace/coverage/default/0.sram_ctrl_alert_test.244402854 |
|
|
Jun 10 06:07:44 PM PDT 24 |
Jun 10 06:07:45 PM PDT 24 |
30552604 ps |
| T798 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2381144473 |
|
|
Jun 10 06:10:57 PM PDT 24 |
Jun 10 06:12:29 PM PDT 24 |
609134802 ps |
| T799 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3931891358 |
|
|
Jun 10 06:11:49 PM PDT 24 |
Jun 10 06:35:03 PM PDT 24 |
8119487329 ps |
| T800 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2572332769 |
|
|
Jun 10 06:11:49 PM PDT 24 |
Jun 10 06:13:38 PM PDT 24 |
789111859 ps |
| T801 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.4021138387 |
|
|
Jun 10 06:13:24 PM PDT 24 |
Jun 10 06:13:25 PM PDT 24 |
87794912 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2163216881 |
|
|
Jun 10 06:11:30 PM PDT 24 |
Jun 10 06:11:31 PM PDT 24 |
30391919 ps |
| T803 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3687561966 |
|
|
Jun 10 06:21:39 PM PDT 24 |
Jun 10 06:22:42 PM PDT 24 |
2026738335 ps |
| T804 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3325968562 |
|
|
Jun 10 06:20:19 PM PDT 24 |
Jun 10 06:20:20 PM PDT 24 |
13633737 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.789428756 |
|
|
Jun 10 06:12:52 PM PDT 24 |
Jun 10 06:13:03 PM PDT 24 |
454775917 ps |
| T806 |
/workspace/coverage/default/26.sram_ctrl_executable.2491825575 |
|
|
Jun 10 06:15:32 PM PDT 24 |
Jun 10 06:24:14 PM PDT 24 |
4072885994 ps |
| T807 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1962217363 |
|
|
Jun 10 06:21:29 PM PDT 24 |
Jun 10 06:21:39 PM PDT 24 |
455331193 ps |
| T808 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.2540183543 |
|
|
Jun 10 06:14:07 PM PDT 24 |
Jun 10 06:14:08 PM PDT 24 |
240800671 ps |
| T809 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2649232681 |
|
|
Jun 10 06:16:30 PM PDT 24 |
Jun 10 06:25:15 PM PDT 24 |
2351281406 ps |
| T810 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2570084857 |
|
|
Jun 10 06:19:30 PM PDT 24 |
Jun 10 06:19:37 PM PDT 24 |
681404742 ps |
| T811 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2852367059 |
|
|
Jun 10 06:20:39 PM PDT 24 |
Jun 10 06:21:27 PM PDT 24 |
200444946 ps |
| T812 |
/workspace/coverage/default/2.sram_ctrl_executable.387800519 |
|
|
Jun 10 06:08:19 PM PDT 24 |
Jun 10 06:21:51 PM PDT 24 |
5390126134 ps |
| T813 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2346962922 |
|
|
Jun 10 06:07:29 PM PDT 24 |
Jun 10 06:12:45 PM PDT 24 |
4100459912 ps |
| T814 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.125977219 |
|
|
Jun 10 06:21:38 PM PDT 24 |
Jun 10 06:23:14 PM PDT 24 |
473134822 ps |
| T815 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3539715208 |
|
|
Jun 10 06:14:07 PM PDT 24 |
Jun 10 06:14:13 PM PDT 24 |
580372939 ps |
| T816 |
/workspace/coverage/default/5.sram_ctrl_regwen.3219792848 |
|
|
Jun 10 06:09:29 PM PDT 24 |
Jun 10 06:13:59 PM PDT 24 |
30320388587 ps |
| T817 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2827187763 |
|
|
Jun 10 06:11:17 PM PDT 24 |
Jun 10 06:33:01 PM PDT 24 |
125808783680 ps |
| T818 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1516807252 |
|
|
Jun 10 06:16:49 PM PDT 24 |
Jun 10 06:19:05 PM PDT 24 |
123341968 ps |
| T819 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3864845619 |
|
|
Jun 10 06:11:12 PM PDT 24 |
Jun 10 06:11:15 PM PDT 24 |
829467932 ps |
| T820 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2865475877 |
|
|
Jun 10 06:15:18 PM PDT 24 |
Jun 10 06:21:58 PM PDT 24 |
73572386478 ps |
| T821 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2531208987 |
|
|
Jun 10 06:19:04 PM PDT 24 |
Jun 10 07:00:06 PM PDT 24 |
8905501585 ps |
| T822 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3022138140 |
|
|
Jun 10 06:13:00 PM PDT 24 |
Jun 10 06:34:22 PM PDT 24 |
3681058421 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3320426118 |
|
|
Jun 10 06:21:16 PM PDT 24 |
Jun 10 07:54:51 PM PDT 24 |
237022274196 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2289063178 |
|
|
Jun 10 06:17:37 PM PDT 24 |
Jun 10 06:17:38 PM PDT 24 |
12766780 ps |
| T825 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.527909730 |
|
|
Jun 10 06:12:34 PM PDT 24 |
Jun 10 06:12:36 PM PDT 24 |
31490463 ps |
| T826 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3060085303 |
|
|
Jun 10 06:13:26 PM PDT 24 |
Jun 10 06:18:19 PM PDT 24 |
3007362362 ps |
| T827 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.4010061880 |
|
|
Jun 10 06:21:43 PM PDT 24 |
Jun 10 06:21:50 PM PDT 24 |
470081274 ps |
| T828 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1706338209 |
|
|
Jun 10 06:18:14 PM PDT 24 |
Jun 10 06:32:38 PM PDT 24 |
8311071860 ps |
| T829 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1906187284 |
|
|
Jun 10 06:11:33 PM PDT 24 |
Jun 10 07:14:32 PM PDT 24 |
201833202830 ps |
| T830 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.665623728 |
|
|
Jun 10 06:13:35 PM PDT 24 |
Jun 10 06:13:46 PM PDT 24 |
345381466 ps |
| T831 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.462842791 |
|
|
Jun 10 06:16:07 PM PDT 24 |
Jun 10 06:16:14 PM PDT 24 |
172709230 ps |
| T832 |
/workspace/coverage/default/31.sram_ctrl_bijection.1183784140 |
|
|
Jun 10 06:16:41 PM PDT 24 |
Jun 10 06:17:36 PM PDT 24 |
5042554536 ps |
| T833 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3606438043 |
|
|
Jun 10 06:16:01 PM PDT 24 |
Jun 10 06:16:10 PM PDT 24 |
1051285600 ps |
| T834 |
/workspace/coverage/default/3.sram_ctrl_bijection.623148977 |
|
|
Jun 10 06:08:34 PM PDT 24 |
Jun 10 06:09:24 PM PDT 24 |
9795560674 ps |
| T835 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3541173082 |
|
|
Jun 10 06:20:39 PM PDT 24 |
Jun 10 06:20:43 PM PDT 24 |
563788518 ps |
| T836 |
/workspace/coverage/default/4.sram_ctrl_partial_access.346871743 |
|
|
Jun 10 06:09:03 PM PDT 24 |
Jun 10 06:09:05 PM PDT 24 |
172769887 ps |
| T837 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2145044142 |
|
|
Jun 10 06:08:18 PM PDT 24 |
Jun 10 06:08:27 PM PDT 24 |
1041157675 ps |
| T838 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3115895871 |
|
|
Jun 10 06:10:05 PM PDT 24 |
Jun 10 06:11:23 PM PDT 24 |
3362769691 ps |
| T839 |
/workspace/coverage/default/45.sram_ctrl_stress_all.134421099 |
|
|
Jun 10 06:20:48 PM PDT 24 |
Jun 10 07:37:05 PM PDT 24 |
120204746963 ps |
| T840 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1425609685 |
|
|
Jun 10 06:18:51 PM PDT 24 |
Jun 10 06:18:52 PM PDT 24 |
55015565 ps |
| T841 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.94728121 |
|
|
Jun 10 06:12:30 PM PDT 24 |
Jun 10 06:15:18 PM PDT 24 |
300612154 ps |
| T842 |
/workspace/coverage/default/23.sram_ctrl_bijection.4061096836 |
|
|
Jun 10 06:14:44 PM PDT 24 |
Jun 10 06:16:00 PM PDT 24 |
4332126794 ps |
| T843 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3183887260 |
|
|
Jun 10 06:14:54 PM PDT 24 |
Jun 10 06:14:55 PM PDT 24 |
127736916 ps |
| T844 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1764161356 |
|
|
Jun 10 06:15:21 PM PDT 24 |
Jun 10 06:20:36 PM PDT 24 |
1503374392 ps |
| T845 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3290199289 |
|
|
Jun 10 06:18:19 PM PDT 24 |
Jun 10 06:26:41 PM PDT 24 |
3690662665 ps |
| T846 |
/workspace/coverage/default/16.sram_ctrl_stress_all.4121901908 |
|
|
Jun 10 06:13:08 PM PDT 24 |
Jun 10 06:42:26 PM PDT 24 |
5650992183 ps |
| T847 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3884959764 |
|
|
Jun 10 06:17:42 PM PDT 24 |
Jun 10 06:21:50 PM PDT 24 |
8306515266 ps |
| T848 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1998133275 |
|
|
Jun 10 06:18:53 PM PDT 24 |
Jun 10 06:22:21 PM PDT 24 |
710926879 ps |
| T849 |
/workspace/coverage/default/4.sram_ctrl_smoke.1846926684 |
|
|
Jun 10 06:09:00 PM PDT 24 |
Jun 10 06:09:16 PM PDT 24 |
946617518 ps |
| T850 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1039822321 |
|
|
Jun 10 06:17:53 PM PDT 24 |
Jun 10 06:18:06 PM PDT 24 |
3281696716 ps |
| T851 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3421885842 |
|
|
Jun 10 06:13:55 PM PDT 24 |
Jun 10 06:18:32 PM PDT 24 |
2806381197 ps |
| T852 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.809813814 |
|
|
Jun 10 06:19:09 PM PDT 24 |
Jun 10 06:19:23 PM PDT 24 |
13054906140 ps |
| T853 |
/workspace/coverage/default/41.sram_ctrl_bijection.62448227 |
|
|
Jun 10 06:19:40 PM PDT 24 |
Jun 10 06:20:24 PM PDT 24 |
7302072206 ps |
| T854 |
/workspace/coverage/default/28.sram_ctrl_bijection.667118293 |
|
|
Jun 10 06:15:57 PM PDT 24 |
Jun 10 06:17:00 PM PDT 24 |
11449465710 ps |
| T855 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3157801519 |
|
|
Jun 10 06:10:29 PM PDT 24 |
Jun 10 06:10:35 PM PDT 24 |
1536770966 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_stress_all.3816912467 |
|
|
Jun 10 06:14:37 PM PDT 24 |
Jun 10 06:36:22 PM PDT 24 |
20915339225 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_smoke.3173469994 |
|
|
Jun 10 06:13:38 PM PDT 24 |
Jun 10 06:13:55 PM PDT 24 |
483522534 ps |
| T858 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2955369016 |
|
|
Jun 10 06:12:42 PM PDT 24 |
Jun 10 06:14:24 PM PDT 24 |
2920444164 ps |
| T859 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2652534298 |
|
|
Jun 10 06:14:55 PM PDT 24 |
Jun 10 06:14:59 PM PDT 24 |
302365583 ps |
| T860 |
/workspace/coverage/default/7.sram_ctrl_regwen.3582717601 |
|
|
Jun 10 06:10:13 PM PDT 24 |
Jun 10 06:20:50 PM PDT 24 |
6579834975 ps |
| T861 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.356109912 |
|
|
Jun 10 06:21:40 PM PDT 24 |
Jun 10 06:25:13 PM PDT 24 |
9786720381 ps |
| T862 |
/workspace/coverage/default/33.sram_ctrl_bijection.2168578008 |
|
|
Jun 10 06:17:21 PM PDT 24 |
Jun 10 06:18:19 PM PDT 24 |
2545486311 ps |
| T863 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3067406620 |
|
|
Jun 10 06:20:11 PM PDT 24 |
Jun 10 06:20:14 PM PDT 24 |
402707376 ps |
| T864 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.598435803 |
|
|
Jun 10 06:14:08 PM PDT 24 |
Jun 10 06:39:00 PM PDT 24 |
36139312813 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2700221807 |
|
|
Jun 10 06:21:15 PM PDT 24 |
Jun 10 06:23:01 PM PDT 24 |
1406134310 ps |
| T866 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1512960411 |
|
|
Jun 10 06:16:16 PM PDT 24 |
Jun 10 06:21:36 PM PDT 24 |
14026708317 ps |
| T867 |
/workspace/coverage/default/34.sram_ctrl_smoke.3691652704 |
|
|
Jun 10 06:17:41 PM PDT 24 |
Jun 10 06:17:45 PM PDT 24 |
70548191 ps |
| T868 |
/workspace/coverage/default/31.sram_ctrl_executable.450363308 |
|
|
Jun 10 06:16:55 PM PDT 24 |
Jun 10 06:50:08 PM PDT 24 |
17715603606 ps |
| T869 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2935565908 |
|
|
Jun 10 06:08:06 PM PDT 24 |
Jun 10 06:08:07 PM PDT 24 |
34356510 ps |
| T870 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3389241331 |
|
|
Jun 10 06:18:27 PM PDT 24 |
Jun 10 06:20:29 PM PDT 24 |
896940413 ps |
| T871 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.963496554 |
|
|
Jun 10 06:14:28 PM PDT 24 |
Jun 10 06:14:30 PM PDT 24 |
132143313 ps |
| T872 |
/workspace/coverage/default/6.sram_ctrl_stress_all.4197713033 |
|
|
Jun 10 06:09:55 PM PDT 24 |
Jun 10 06:25:03 PM PDT 24 |
11908275461 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3457249451 |
|
|
Jun 10 06:11:38 PM PDT 24 |
Jun 10 06:19:52 PM PDT 24 |
30697613014 ps |
| T874 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3131370520 |
|
|
Jun 10 06:17:40 PM PDT 24 |
Jun 10 06:48:34 PM PDT 24 |
21244345939 ps |
| T875 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3973576527 |
|
|
Jun 10 06:15:30 PM PDT 24 |
Jun 10 06:17:28 PM PDT 24 |
642718234 ps |
| T876 |
/workspace/coverage/default/25.sram_ctrl_alert_test.4251309932 |
|
|
Jun 10 06:15:28 PM PDT 24 |
Jun 10 06:15:29 PM PDT 24 |
47226510 ps |
| T877 |
/workspace/coverage/default/8.sram_ctrl_bijection.649169104 |
|
|
Jun 10 06:10:22 PM PDT 24 |
Jun 10 06:11:02 PM PDT 24 |
2869180953 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_executable.3867265347 |
|
|
Jun 10 06:11:46 PM PDT 24 |
Jun 10 06:23:44 PM PDT 24 |
3329179401 ps |
| T879 |
/workspace/coverage/default/37.sram_ctrl_stress_all.216216772 |
|
|
Jun 10 06:18:54 PM PDT 24 |
Jun 10 06:29:27 PM PDT 24 |
15404743973 ps |
| T880 |
/workspace/coverage/default/41.sram_ctrl_regwen.2708653239 |
|
|
Jun 10 06:19:45 PM PDT 24 |
Jun 10 06:29:21 PM PDT 24 |
2665999050 ps |
| T881 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2687865034 |
|
|
Jun 10 06:14:17 PM PDT 24 |
Jun 10 06:14:18 PM PDT 24 |
57757616 ps |
| T882 |
/workspace/coverage/default/27.sram_ctrl_bijection.3599211349 |
|
|
Jun 10 06:15:44 PM PDT 24 |
Jun 10 06:16:14 PM PDT 24 |
1427297872 ps |
| T883 |
/workspace/coverage/default/42.sram_ctrl_bijection.3227696187 |
|
|
Jun 10 06:19:49 PM PDT 24 |
Jun 10 06:20:40 PM PDT 24 |
12895680288 ps |
| T884 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1968314298 |
|
|
Jun 10 06:21:31 PM PDT 24 |
Jun 10 06:21:32 PM PDT 24 |
57228720 ps |
| T885 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.714955817 |
|
|
Jun 10 06:15:44 PM PDT 24 |
Jun 10 06:20:57 PM PDT 24 |
3169781514 ps |
| T886 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4059047403 |
|
|
Jun 10 06:19:15 PM PDT 24 |
Jun 10 06:21:26 PM PDT 24 |
582861532 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1766877116 |
|
|
Jun 10 06:13:24 PM PDT 24 |
Jun 10 06:14:21 PM PDT 24 |
619622680 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_smoke.2596614592 |
|
|
Jun 10 06:11:38 PM PDT 24 |
Jun 10 06:11:46 PM PDT 24 |
381571451 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2470704985 |
|
|
Jun 10 06:11:49 PM PDT 24 |
Jun 10 06:11:54 PM PDT 24 |
1629287392 ps |
| T890 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.4088098307 |
|
|
Jun 10 06:09:51 PM PDT 24 |
Jun 10 06:09:56 PM PDT 24 |
74570324 ps |
| T891 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3946701971 |
|
|
Jun 10 06:19:17 PM PDT 24 |
Jun 10 06:25:29 PM PDT 24 |
2145139694 ps |
| T892 |
/workspace/coverage/default/46.sram_ctrl_bijection.3621450625 |
|
|
Jun 10 06:20:50 PM PDT 24 |
Jun 10 06:22:06 PM PDT 24 |
18179114981 ps |
| T893 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3549221473 |
|
|
Jun 10 06:16:22 PM PDT 24 |
Jun 10 06:16:30 PM PDT 24 |
652798107 ps |
| T894 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3254458246 |
|
|
Jun 10 06:12:46 PM PDT 24 |
Jun 10 06:12:52 PM PDT 24 |
883622509 ps |
| T895 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2008097389 |
|
|
Jun 10 06:18:18 PM PDT 24 |
Jun 10 06:18:30 PM PDT 24 |
659588643 ps |
| T896 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2370701116 |
|
|
Jun 10 06:15:55 PM PDT 24 |
Jun 10 06:32:16 PM PDT 24 |
63148517988 ps |
| T897 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1191724986 |
|
|
Jun 10 06:20:48 PM PDT 24 |
Jun 10 06:20:52 PM PDT 24 |
98850460 ps |
| T898 |
/workspace/coverage/default/47.sram_ctrl_bijection.936268428 |
|
|
Jun 10 06:21:13 PM PDT 24 |
Jun 10 06:22:25 PM PDT 24 |
3956786397 ps |
| T899 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1823788327 |
|
|
Jun 10 06:13:37 PM PDT 24 |
Jun 10 06:13:56 PM PDT 24 |
1266889501 ps |
| T900 |
/workspace/coverage/default/48.sram_ctrl_stress_all.15588101 |
|
|
Jun 10 06:21:31 PM PDT 24 |
Jun 10 07:57:06 PM PDT 24 |
247251430788 ps |
| T901 |
/workspace/coverage/default/43.sram_ctrl_smoke.95824946 |
|
|
Jun 10 06:20:02 PM PDT 24 |
Jun 10 06:21:22 PM PDT 24 |
1017131577 ps |
| T902 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2454868468 |
|
|
Jun 10 06:08:04 PM PDT 24 |
Jun 10 06:13:56 PM PDT 24 |
1567330689 ps |
| T903 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1712132863 |
|
|
Jun 10 06:20:38 PM PDT 24 |
Jun 10 06:20:44 PM PDT 24 |
407773695 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1899356795 |
|
|
Jun 10 06:09:11 PM PDT 24 |
Jun 10 06:09:12 PM PDT 24 |
33998612 ps |
| T905 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1420549183 |
|
|
Jun 10 06:07:56 PM PDT 24 |
Jun 10 06:09:39 PM PDT 24 |
2238393161 ps |
| T906 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.993704598 |
|
|
Jun 10 06:17:44 PM PDT 24 |
Jun 10 06:23:25 PM PDT 24 |
12961908093 ps |
| T907 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.288475063 |
|
|
Jun 10 06:15:59 PM PDT 24 |
Jun 10 06:16:18 PM PDT 24 |
179723007 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2027488606 |
|
|
Jun 10 06:14:59 PM PDT 24 |
Jun 10 06:15:06 PM PDT 24 |
662379289 ps |
| T909 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3056481397 |
|
|
Jun 10 06:13:55 PM PDT 24 |
Jun 10 06:15:23 PM PDT 24 |
736831455 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4166132947 |
|
|
Jun 10 06:20:55 PM PDT 24 |
Jun 10 06:24:43 PM PDT 24 |
14143068071 ps |
| T911 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3393202691 |
|
|
Jun 10 06:18:40 PM PDT 24 |
Jun 10 06:27:21 PM PDT 24 |
3691787204 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3703570937 |
|
|
Jun 10 06:21:44 PM PDT 24 |
Jun 10 06:21:45 PM PDT 24 |
28708993 ps |
| T913 |
/workspace/coverage/default/25.sram_ctrl_regwen.1601146388 |
|
|
Jun 10 06:15:25 PM PDT 24 |
Jun 10 06:27:13 PM PDT 24 |
17537123976 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1029545960 |
|
|
Jun 10 06:16:45 PM PDT 24 |
Jun 10 06:31:01 PM PDT 24 |
137739945391 ps |
| T915 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.49858170 |
|
|
Jun 10 06:08:10 PM PDT 24 |
Jun 10 06:22:32 PM PDT 24 |
7931660844 ps |
| T916 |
/workspace/coverage/default/19.sram_ctrl_regwen.1159887262 |
|
|
Jun 10 06:13:48 PM PDT 24 |
Jun 10 06:28:16 PM PDT 24 |
35811761764 ps |
| T917 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1206321218 |
|
|
Jun 10 06:09:48 PM PDT 24 |
Jun 10 06:23:57 PM PDT 24 |
36047012961 ps |
| T918 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.446684473 |
|
|
Jun 10 06:12:42 PM PDT 24 |
Jun 10 06:18:51 PM PDT 24 |
18910506386 ps |
| T919 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3391437417 |
|
|
Jun 10 06:13:51 PM PDT 24 |
Jun 10 06:19:43 PM PDT 24 |
4480563175 ps |
| T920 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2102868763 |
|
|
Jun 10 06:19:39 PM PDT 24 |
Jun 10 06:25:57 PM PDT 24 |
10221532097 ps |
| T921 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2735728996 |
|
|
Jun 10 06:13:15 PM PDT 24 |
Jun 10 06:13:24 PM PDT 24 |
1590188959 ps |
| T922 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2624903516 |
|
|
Jun 10 06:17:04 PM PDT 24 |
Jun 10 06:18:52 PM PDT 24 |
140042512 ps |
| T923 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2286778412 |
|
|
Jun 10 06:12:18 PM PDT 24 |
Jun 10 06:40:01 PM PDT 24 |
37759701591 ps |
| T924 |
/workspace/coverage/default/33.sram_ctrl_executable.822653892 |
|
|
Jun 10 06:17:29 PM PDT 24 |
Jun 10 06:21:38 PM PDT 24 |
485411901 ps |
| T925 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1785447248 |
|
|
Jun 10 06:21:03 PM PDT 24 |
Jun 10 06:21:10 PM PDT 24 |
194767854 ps |
| T926 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1113952809 |
|
|
Jun 10 06:15:47 PM PDT 24 |
Jun 10 06:35:45 PM PDT 24 |
41391884937 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2282025410 |
|
|
Jun 10 06:16:32 PM PDT 24 |
Jun 10 06:23:21 PM PDT 24 |
33588324038 ps |
| T928 |
/workspace/coverage/default/46.sram_ctrl_regwen.3445446130 |
|
|
Jun 10 06:20:59 PM PDT 24 |
Jun 10 06:26:41 PM PDT 24 |
2244090235 ps |
| T929 |
/workspace/coverage/default/23.sram_ctrl_executable.196806875 |
|
|
Jun 10 06:14:52 PM PDT 24 |
Jun 10 06:25:23 PM PDT 24 |
19395504129 ps |
| T930 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2149261774 |
|
|
Jun 10 05:55:28 PM PDT 24 |
Jun 10 05:55:30 PM PDT 24 |
175720936 ps |
| T50 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4041567522 |
|
|
Jun 10 05:55:52 PM PDT 24 |
Jun 10 05:55:54 PM PDT 24 |
29235599 ps |
| T51 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4034728415 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:43 PM PDT 24 |
148584901 ps |
| T52 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3576419172 |
|
|
Jun 10 05:55:25 PM PDT 24 |
Jun 10 05:55:26 PM PDT 24 |
27359367 ps |
| T59 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3163409813 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:51 PM PDT 24 |
13708506 ps |
| T931 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3494082650 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:45 PM PDT 24 |
124857809 ps |
| T47 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2214883855 |
|
|
Jun 10 05:55:56 PM PDT 24 |
Jun 10 05:55:58 PM PDT 24 |
177140362 ps |
| T932 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2934586438 |
|
|
Jun 10 05:55:43 PM PDT 24 |
Jun 10 05:55:47 PM PDT 24 |
188983956 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3745432790 |
|
|
Jun 10 05:55:31 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
823139762 ps |
| T61 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1626501129 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
222624753 ps |
| T933 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3751955195 |
|
|
Jun 10 05:55:33 PM PDT 24 |
Jun 10 05:55:35 PM PDT 24 |
31883059 ps |
| T62 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1452178692 |
|
|
Jun 10 05:55:55 PM PDT 24 |
Jun 10 05:55:56 PM PDT 24 |
34042746 ps |
| T63 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1809147451 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:44 PM PDT 24 |
16095281 ps |
| T48 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4138133132 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:45 PM PDT 24 |
477810005 ps |
| T934 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1330918061 |
|
|
Jun 10 05:55:57 PM PDT 24 |
Jun 10 05:55:58 PM PDT 24 |
75047192 ps |
| T935 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.905889903 |
|
|
Jun 10 05:55:28 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
146264918 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.663721013 |
|
|
Jun 10 05:55:55 PM PDT 24 |
Jun 10 05:55:57 PM PDT 24 |
944757826 ps |
| T936 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3741634194 |
|
|
Jun 10 05:55:37 PM PDT 24 |
Jun 10 05:55:38 PM PDT 24 |
21895768 ps |
| T49 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.623324291 |
|
|
Jun 10 05:55:48 PM PDT 24 |
Jun 10 05:55:50 PM PDT 24 |
409654395 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2367257097 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:51 PM PDT 24 |
17400459 ps |
| T937 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3547884107 |
|
|
Jun 10 05:55:37 PM PDT 24 |
Jun 10 05:55:38 PM PDT 24 |
54514738 ps |
| T938 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3789506033 |
|
|
Jun 10 05:55:36 PM PDT 24 |
Jun 10 05:55:37 PM PDT 24 |
46906487 ps |
| T114 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1951035653 |
|
|
Jun 10 05:55:38 PM PDT 24 |
Jun 10 05:55:40 PM PDT 24 |
107918303 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2621881275 |
|
|
Jun 10 05:55:46 PM PDT 24 |
Jun 10 05:55:48 PM PDT 24 |
1377275762 ps |
| T939 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1912912177 |
|
|
Jun 10 05:55:40 PM PDT 24 |
Jun 10 05:55:44 PM PDT 24 |
574878691 ps |
| T66 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2346201958 |
|
|
Jun 10 05:55:36 PM PDT 24 |
Jun 10 05:55:41 PM PDT 24 |
1096621441 ps |
| T115 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1820478080 |
|
|
Jun 10 05:55:31 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
188999007 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3313518982 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:50 PM PDT 24 |
36353390 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1308549948 |
|
|
Jun 10 05:55:54 PM PDT 24 |
Jun 10 05:55:59 PM PDT 24 |
359800719 ps |
| T942 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2424561079 |
|
|
Jun 10 05:55:27 PM PDT 24 |
Jun 10 05:55:28 PM PDT 24 |
26559822 ps |
| T90 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.884681982 |
|
|
Jun 10 05:55:45 PM PDT 24 |
Jun 10 05:55:47 PM PDT 24 |
15576711 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2292385219 |
|
|
Jun 10 05:55:33 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
46190743 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1103925153 |
|
|
Jun 10 05:55:40 PM PDT 24 |
Jun 10 05:55:42 PM PDT 24 |
229514048 ps |
| T73 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.793263705 |
|
|
Jun 10 05:55:52 PM PDT 24 |
Jun 10 05:55:53 PM PDT 24 |
27184346 ps |
| T123 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.798679880 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:35 PM PDT 24 |
250520076 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1073325258 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
19684268 ps |
| T944 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3095633401 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
80956124 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.993963677 |
|
|
Jun 10 05:55:45 PM PDT 24 |
Jun 10 05:55:46 PM PDT 24 |
68552067 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2028604172 |
|
|
Jun 10 05:55:29 PM PDT 24 |
Jun 10 05:55:30 PM PDT 24 |
20295278 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.492628000 |
|
|
Jun 10 05:55:38 PM PDT 24 |
Jun 10 05:55:43 PM PDT 24 |
141164566 ps |
| T948 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3045844144 |
|
|
Jun 10 05:55:52 PM PDT 24 |
Jun 10 05:55:54 PM PDT 24 |
453171532 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3180476785 |
|
|
Jun 10 05:55:31 PM PDT 24 |
Jun 10 05:55:32 PM PDT 24 |
108307880 ps |
| T74 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1472875597 |
|
|
Jun 10 05:55:36 PM PDT 24 |
Jun 10 05:55:38 PM PDT 24 |
1069699976 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.935291043 |
|
|
Jun 10 05:55:39 PM PDT 24 |
Jun 10 05:55:41 PM PDT 24 |
387508180 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3996611655 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:36 PM PDT 24 |
20504056 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.892934239 |
|
|
Jun 10 05:55:28 PM PDT 24 |
Jun 10 05:55:29 PM PDT 24 |
13484702 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3146094465 |
|
|
Jun 10 05:55:52 PM PDT 24 |
Jun 10 05:55:53 PM PDT 24 |
37009978 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.12375906 |
|
|
Jun 10 05:55:45 PM PDT 24 |
Jun 10 05:55:48 PM PDT 24 |
297385474 ps |
| T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4242090343 |
|
|
Jun 10 05:55:29 PM PDT 24 |
Jun 10 05:55:31 PM PDT 24 |
231974714 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.676638084 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:36 PM PDT 24 |
26745952 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.475254587 |
|
|
Jun 10 05:55:51 PM PDT 24 |
Jun 10 05:55:52 PM PDT 24 |
45056368 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4157147082 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:46 PM PDT 24 |
492852362 ps |
| T116 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3039428410 |
|
|
Jun 10 05:55:35 PM PDT 24 |
Jun 10 05:55:39 PM PDT 24 |
209464503 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2577982214 |
|
|
Jun 10 05:55:35 PM PDT 24 |
Jun 10 05:55:37 PM PDT 24 |
80427168 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3641721797 |
|
|
Jun 10 05:55:44 PM PDT 24 |
Jun 10 05:55:46 PM PDT 24 |
1127594958 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.274610260 |
|
|
Jun 10 05:55:36 PM PDT 24 |
Jun 10 05:55:39 PM PDT 24 |
905638669 ps |
| T958 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.777924922 |
|
|
Jun 10 05:55:47 PM PDT 24 |
Jun 10 05:55:48 PM PDT 24 |
56896289 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1840829002 |
|
|
Jun 10 05:55:57 PM PDT 24 |
Jun 10 05:55:58 PM PDT 24 |
24750220 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.748678518 |
|
|
Jun 10 05:55:54 PM PDT 24 |
Jun 10 05:56:07 PM PDT 24 |
360171563 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.948226737 |
|
|
Jun 10 05:55:43 PM PDT 24 |
Jun 10 05:55:47 PM PDT 24 |
322045494 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2926756351 |
|
|
Jun 10 05:55:47 PM PDT 24 |
Jun 10 05:55:49 PM PDT 24 |
168840411 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.179044799 |
|
|
Jun 10 05:55:46 PM PDT 24 |
Jun 10 05:55:48 PM PDT 24 |
287127286 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1895503223 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
66293369 ps |
| T964 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4144593372 |
|
|
Jun 10 05:55:35 PM PDT 24 |
Jun 10 05:55:37 PM PDT 24 |
109332332 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3283310725 |
|
|
Jun 10 05:55:37 PM PDT 24 |
Jun 10 05:55:39 PM PDT 24 |
49108893 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1528675656 |
|
|
Jun 10 05:55:38 PM PDT 24 |
Jun 10 05:55:41 PM PDT 24 |
139970940 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.574123641 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:50 PM PDT 24 |
25710843 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4290442274 |
|
|
Jun 10 05:55:44 PM PDT 24 |
Jun 10 05:55:45 PM PDT 24 |
13068687 ps |
| T121 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3880386047 |
|
|
Jun 10 05:55:35 PM PDT 24 |
Jun 10 05:55:38 PM PDT 24 |
410492331 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.560949644 |
|
|
Jun 10 05:55:31 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
35591292 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1237346435 |
|
|
Jun 10 05:55:53 PM PDT 24 |
Jun 10 05:55:54 PM PDT 24 |
11436245 ps |
| T970 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3618070143 |
|
|
Jun 10 05:55:51 PM PDT 24 |
Jun 10 05:55:52 PM PDT 24 |
24264405 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.149563722 |
|
|
Jun 10 05:55:30 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
2472536452 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3854129896 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:46 PM PDT 24 |
74233465 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2979183184 |
|
|
Jun 10 05:55:47 PM PDT 24 |
Jun 10 05:55:51 PM PDT 24 |
47433217 ps |
| T125 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3471429208 |
|
|
Jun 10 05:55:51 PM PDT 24 |
Jun 10 05:55:54 PM PDT 24 |
357661560 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2455508023 |
|
|
Jun 10 05:55:46 PM PDT 24 |
Jun 10 05:55:49 PM PDT 24 |
32439278 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3342460223 |
|
|
Jun 10 05:55:46 PM PDT 24 |
Jun 10 05:55:49 PM PDT 24 |
473170896 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.508279170 |
|
|
Jun 10 05:55:52 PM PDT 24 |
Jun 10 05:56:00 PM PDT 24 |
151444814 ps |
| T974 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2846802780 |
|
|
Jun 10 05:55:45 PM PDT 24 |
Jun 10 05:55:50 PM PDT 24 |
228079930 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1340063148 |
|
|
Jun 10 05:55:47 PM PDT 24 |
Jun 10 05:55:51 PM PDT 24 |
2765438427 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.425954370 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:37 PM PDT 24 |
265477449 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1264595885 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:50 PM PDT 24 |
55900285 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2684363435 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:36 PM PDT 24 |
100049307 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4146115939 |
|
|
Jun 10 05:55:55 PM PDT 24 |
Jun 10 05:55:57 PM PDT 24 |
159511025 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1905178438 |
|
|
Jun 10 05:55:53 PM PDT 24 |
Jun 10 05:55:57 PM PDT 24 |
476904189 ps |
| T118 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2117771976 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:35 PM PDT 24 |
166142636 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.610160800 |
|
|
Jun 10 05:55:44 PM PDT 24 |
Jun 10 05:55:46 PM PDT 24 |
42718640 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1483885760 |
|
|
Jun 10 05:55:57 PM PDT 24 |
Jun 10 05:55:59 PM PDT 24 |
337389369 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1046283272 |
|
|
Jun 10 05:55:31 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
81748931 ps |
| T84 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.491047214 |
|
|
Jun 10 05:55:42 PM PDT 24 |
Jun 10 05:55:47 PM PDT 24 |
875944122 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2653609349 |
|
|
Jun 10 05:55:38 PM PDT 24 |
Jun 10 05:55:43 PM PDT 24 |
134768300 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3352305408 |
|
|
Jun 10 05:55:30 PM PDT 24 |
Jun 10 05:55:31 PM PDT 24 |
262792848 ps |
| T985 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2181904908 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:39 PM PDT 24 |
240433235 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4015151044 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:36 PM PDT 24 |
110026677 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2489403477 |
|
|
Jun 10 05:55:52 PM PDT 24 |
Jun 10 05:55:55 PM PDT 24 |
624310783 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3559153489 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
24720131 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1518510617 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:50 PM PDT 24 |
28419837 ps |
| T989 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2369648246 |
|
|
Jun 10 05:55:57 PM PDT 24 |
Jun 10 05:56:00 PM PDT 24 |
51827151 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3527623033 |
|
|
Jun 10 05:55:34 PM PDT 24 |
Jun 10 05:55:35 PM PDT 24 |
21733125 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2718519100 |
|
|
Jun 10 05:55:31 PM PDT 24 |
Jun 10 05:55:36 PM PDT 24 |
502770857 ps |
| T992 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3183445996 |
|
|
Jun 10 05:55:35 PM PDT 24 |
Jun 10 05:55:37 PM PDT 24 |
150144046 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4136986385 |
|
|
Jun 10 05:55:47 PM PDT 24 |
Jun 10 05:55:49 PM PDT 24 |
29431489 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3563012099 |
|
|
Jun 10 05:55:49 PM PDT 24 |
Jun 10 05:55:51 PM PDT 24 |
96792636 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2225191913 |
|
|
Jun 10 05:55:33 PM PDT 24 |
Jun 10 05:55:37 PM PDT 24 |
1468306731 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3349685245 |
|
|
Jun 10 05:55:45 PM PDT 24 |
Jun 10 05:55:48 PM PDT 24 |
41643635 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1874896964 |
|
|
Jun 10 05:55:33 PM PDT 24 |
Jun 10 05:55:34 PM PDT 24 |
24257673 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4126172927 |
|
|
Jun 10 05:55:27 PM PDT 24 |
Jun 10 05:55:28 PM PDT 24 |
39400658 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3775691300 |
|
|
Jun 10 05:55:32 PM PDT 24 |
Jun 10 05:55:33 PM PDT 24 |
33745697 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3767765960 |
|
|
Jun 10 05:55:38 PM PDT 24 |
Jun 10 05:55:40 PM PDT 24 |
66527906 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1804823478 |
|
|
Jun 10 05:55:41 PM PDT 24 |
Jun 10 05:55:43 PM PDT 24 |
250829961 ps |